From d509ee55b6b91270b1369311e20cbc717ad7b4b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 14 Jan 2021 00:09:11 +0100 Subject: soc/intel/apl: drop LPC pad configuration code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop LPC pad configuration code since all boards now do pad configuration on their own. The comment about LPC_CLKRUNB when using eSPI is moved to `Documentation/getting_started/gpio.md`. Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/getting_started/gpio.md | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 13aeed5bd2..d4e8ca7df4 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -129,3 +129,13 @@ If no pullup or pulldown is declared with these, they may end up "floating", i.e., not at logical high or logical low. This can cause problems such as unwanted power consumption or not reading the pin correctly, if it was intended to be strapped. + +## Pad-related known issues and workarounds + +### LPC_CLKRUNB blocks S0ix states when board uses eSPI + +When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode. +Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up +enable/disable etc are ignored. Leaving this pin in native mode will keep the +LPC Controller awake and prevent S0ix entry. This issues is know at least on +Apollolake and Geminilake. -- cgit v1.2.3