From 66decf16446eeb8d3b2da93d0b0086a583bc17bf Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 4 Feb 2016 11:21:33 -0800 Subject: Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/Board/board.html | 25 ++++++++++++++++++++ Documentation/Intel/SoC/soc.html | 44 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 28 +++++++++++++++++++++++ Documentation/Intel/fsp1_1.html | 14 ++++++++++++ 4 files changed, 111 insertions(+) (limited to 'Documentation') diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index 8de854b64f..d50ff4e74f 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -14,6 +14,7 @@

  1. Required Files
    2. +
  2. Enable Serial Output
@@ -77,6 +78,30 @@ +
+

Enable Serial Output

+

+ Use the following steps to enable serial output: +

+
    +
  1. Implement the car_mainboard_pre_console_init routine in the com_init.c + file: +
      +
    1. Power on and enable the UART controller
      2. +
    2. Connect the UART receive and transmit data lines to the + appropriate SoC pins +
      3. +
    +
    2. +
  2. Add Makefile.inc +
      +
    1. Add com_init.c to romstage
      2. +
    +
    3. +
+ + +

Modified: 31 January 2016

diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 679e022f64..0b0615d049 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -19,6 +19,11 @@
  • Early Debug
  • Bootblock
  • TempRamInit
    • +
  • Romstage +
      +
    1. Enable Serial Output"
      2. +
    +
    • @@ -284,6 +289,45 @@ Use the following steps to debug the call to TempRamInit: +
    +

    Romstage

    + +

    Serial Output

    +

    + The following steps add the serial output support for romstage: +

    +
      +
    1. Create the romstage subdirectory
      2. +
    2. Add romstage/romstage.c +
        +
      1. Program the necessary base addresses
        2. +
      2. Disable the TCO
        3. +
      +
      3. +
    3. Add romstage/Makefile.inc +
        +
      1. Add romstage.c to romstage
        2. +
      +
      4. +
    4. Add gpio configuration support if necessary
      5. +
    5. Add the necessary .h files to support the build
      6. +
    6. Update Makefile.inc +
        +
      1. Add the romstage subdirectory
        2. +
      2. Add the gpio configuration support file to romstage
        3. +
      +
      7. +
    7. Set the necessary Kconfig values to enable serial output: +
        +
      • CONFIG_DRIVERS_UART_<driver>=y
        • +
      • CONFIG_CONSOLE_SERIAL=y
        • +
      • CONFIG_UART_FOR_CONSOLE=<port>
        • +
      • CONFIG_CONSOLE_SERIAL_115200=y
        • +
      +
      8. +
    + +

    Modified: 31 January 2016

    diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 2b23b39e23..b90fa96567 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -71,6 +71,17 @@
  • Early Debug
  • Implement and debug the bootblock code
  • Implement and debug the call to TempRamInit
    • +
  • Enable the serial port +
      +
    1. Power on, enable and configure GPIOs for the + debug serial UART +
      2. +
    2. Add the serial outupt + support to romstage +
      3. +
    +
    • +
  • Enable coreboot/FSP debugging
    • @@ -106,6 +117,23 @@ Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit + + + + Board + Where + Testing + + + Serial Port + + SoC Support
    + Enable: src/soc/mainboard/<Board>/com_init.c/car_mainboard_pre_console_init + + Debug serial output works + + + FSP Where diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 456db802a8..0727e7ba20 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -15,6 +15,7 @@
    1. Required Files
    2. Add the FSP Binary File to the coreboot File System
      3. +
    3. Enable coreboot/FSP Debugging

    @@ -57,6 +58,19 @@

    +
    +

    Enable coreboot/FSP Debugging

    +

    + Set the following Kconfig values: +

    +
      +
    • CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage
      • +
    • CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit
      • +
    • CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP
      • +
    • CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit
      • +
    + +

    Modified: 31 January 2016

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