From 4ee073d4769a966e1da0e61575e1b1f9c6ad820a Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 28 Feb 2016 06:22:47 -0800 Subject: Documentation/Intel: More CorebootPayloadPkg documentation Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/SoC/quark.html | 4 +-- Documentation/Intel/SoC/soc.html | 54 +++++++++++++++++++++++++++++++++++- Documentation/Intel/development.html | 13 ++++++++- Documentation/Intel/index.html | 16 ++++++++++- 4 files changed, 82 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index ea704a94c5..5fe3f5ce02 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -47,7 +47,7 @@
-

Quark™ EDK2 CorebootPayloadPkg

+

Quark™ EDK2 CorebootPayloadPkg

Build Instructions:

@@ -214,6 +214,6 @@ Documentation:
-

Modified: 20 February 2016

+

Modified: 24 February 2016

\ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 5a0a442161..2380cdf61e 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -33,6 +33,7 @@
  • ACPI Tables
    • +
  • Legacy Hardware
    • @@ -560,7 +561,7 @@ Use the following steps to debug the call to TempRamInit:

    ACPI Tables

    - One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg. + One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg.

    FADT

    @@ -664,6 +665,57 @@ Use the following steps to debug the call to TempRamInit: + +
    +

    Legacy Hardware

    +

    + One of the payloads that needs legacy hardare is the EDK2 CorebootPayloadPkg. +

    + + + + + + + + + + + + + + + + + + + + + + + +
    PeripheralUse8259 Interrupt VectorIDT Base OffsetInterrupt Handler
    + 8254 + Programmable Interval Timer + + EDK2: PcAtChipsetPkg/8254TimerDxe/Timer.c + 00x340 + TimerInterruptHandler +
    + 8259 + Programmable Interrupt Controller + + EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/8259.c + + Master interrupts: 0, 2 - 7
    + Slave interrupts: 8 - 15
    + Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 +     		+ Master: 0x340, 0x350 - 0x378
    + Slave: 0x380 - 0x3b8
    + Interrupt descriptors are 8 bytes each +     		 
    +

    Modified: 28 February 2016

    diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 74a476fdc0..7b82321266 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -125,6 +125,7 @@
  • Payload and OS Features:
    • @@ -141,6 +142,16 @@ Where Testing + + 8254 Programmable Interval Timer + Legacy hardware support + CorebootPayloadPkg gets to shell prompt + + + 8259 Programmable Interrupt Controller + Legacy hardware support + CorebootPayloadPkg gets to shell prompt + Cache-as-RAM @@ -335,6 +346,6 @@
    -

    Modified: 20 February 2016

    +

    Modified: 24 February 2016

    \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 61d14c861f..4d508bfa61 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -21,6 +21,7 @@

    x86 coreboot Development

    +

    Payload Development

    + + + +

    Documentation

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