From 2326a284ac6a6646a918331425952ece2da723c1 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Sat, 7 Jul 2018 15:54:37 +0200 Subject: riscv: add trampoline in MBR block to support boot mode 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- Documentation/mainboard/sifive/hifive-unleashed.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index c5c015ddc1..1d07cb7df6 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -11,7 +11,7 @@ For general setup instructions, please refer to the [Getting Started Guide]. The following things are still missing from this coreboot port: -- Trampoline in the MBR block to support boot mode 1 +- Support running romstage from flash (fix stack) to support boot mode 1 - CBMEM support - FU540 clock configuration - FU540 RAM init -- cgit v1.2.3