From 8c986ab26358b40863f7404c97e8afbb118789f1 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 18 Jun 2018 13:23:27 +0200 Subject: Documentation: Add cavium SoC and mainboard * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Philipp Deppenwiese --- Documentation/soc/cavium/bootflow.md | 19 +++++ Documentation/soc/cavium/cavium_bootflow.png | Bin 0 -> 116546 bytes Documentation/soc/cavium/cn81xx/index.md | 119 +++++++++++++++++++++++++++ Documentation/soc/cavium/index.md | 8 ++ Documentation/soc/index.md | 1 + 5 files changed, 147 insertions(+) create mode 100644 Documentation/soc/cavium/bootflow.md create mode 100644 Documentation/soc/cavium/cavium_bootflow.png create mode 100644 Documentation/soc/cavium/cn81xx/index.md create mode 100644 Documentation/soc/cavium/index.md (limited to 'Documentation/soc') diff --git a/Documentation/soc/cavium/bootflow.md b/Documentation/soc/cavium/bootflow.md new file mode 100644 index 0000000000..70bf865447 --- /dev/null +++ b/Documentation/soc/cavium/bootflow.md @@ -0,0 +1,19 @@ +# Cavium bootflow + +The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller. +It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get +the position of the bootstage in flash. It then loads 192KiB from flash into +L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as +the signature of the bootstage isn't verified. +The **BOOTROM** can do AES decryption for obfuscation or verify the signature +of the bootstage. Both features aren't used and won't be described any further. + +* The typical position of bootstage in flash is at address **0x20000**. +* The entry point in physical DRAM is at address **0x100000**. + +## Layout + +![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow] + +[cavium_bootflow]: cavium_bootflow.png + diff --git a/Documentation/soc/cavium/cavium_bootflow.png b/Documentation/soc/cavium/cavium_bootflow.png new file mode 100644 index 0000000000..1e9017353c Binary files /dev/null and b/Documentation/soc/cavium/cavium_bootflow.png differ diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md new file mode 100644 index 0000000000..69fe7105ca --- /dev/null +++ b/Documentation/soc/cavium/cn81xx/index.md @@ -0,0 +1,119 @@ +# Cavium CN81xx documentation + +## Reference code + +```eval_rst +The Cavium reference code is called `BDK`_ (board development kit) and is part +of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot. +``` + +## SOC code + +The SOC folder contains functions for: +* TWSI +* UART +* TIMER +* SPI +* MMU +* DRAM +* CLOCK +* GPIO +* Secondary CPUs +* PCI + +All other hardware is initilized by the BDK code, which is invoked from +ramstage. + +## Notes about the hardware + +Cavium SoC do **not** have embedded SRAM. The **BOOTROM** setups the +L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed +location. It then jumps to the firmware. + +```eval_rst +For more details have a look at `Cavium CN8XXX Bootflow`_. +``` + +## CAR setup + +For Cache-as-RAM we only need to lock the cachelines which are used by bootblock +or romstage until DRAM has been set up. At the end of romstage the cachelines +are unlocked and the contents are flushed to DRAM. +Locked cachelines are never evicted. + +The CAR setup is done in '''bootblock_custom.S''' and thus doesn't use the common +aarch64 '''bootblock.S''' code. + +## DRAM setup + +```eval_rst +The DRAM setup is done by the `BDK`_. +``` + +## PCI setup + +The PCI setup is done using the MMCONF mechanism. +Besides configuring device visibility (secure/unsecure) the MSI-X interrupts +needs to be configured. + +## Devicetree patching + +The Linux devicetree needs to be patched, depending on the available hardware +and their configuration. Some values depends on fuses, some on user selectable +configuration. + +The following SoC specific fixes are made: + +1. Fix SCLK +2. Fix UUA refclock +3. Remove unused PEM entries +4. Remove unused QLM entries +5. Set local MAC address + +## CN81xx quirks + +The CN81xx needs some quirks that are not documented or hidden in the code. + +### Violation of PCI spec + +**Problem:** + +* The PCI device 01:01.0 is disabled, but a multifunction device. +* The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot + PCI allocator. + +**Solution:** + +The PCI Bus 0 and 1 are scanned manually in SOC's PCI code. + + +### Crash accessing SLI memory + +**Problem:** + +The SLI memory region decodes to attached PCIe devices. +Accessing the memory region results in 'Data Abort Exception' if the link of the +PCIe device never had been enabled. + +**Solution:** + +Enable the PCIe link at least once. (You can disabling the link and the SLI +memory reads as 0xffffffff.) + + +### RNG Data Abort Exception + +**Problem:** + +'Data Abort Exception' on accessing the enabled RNG. + +**Solution**: + +Read the BDK_RNM_CTL_STATUS register at least once after writing it. + + +```eval_rst +.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK +.. _Cavium CN8XXX Bootflow: ../bootflow.html +.. _BDK: ../../../vendorcode/cavium/bdk.html +``` diff --git a/Documentation/soc/cavium/index.md b/Documentation/soc/cavium/index.md new file mode 100644 index 0000000000..5ccb47f611 --- /dev/null +++ b/Documentation/soc/cavium/index.md @@ -0,0 +1,8 @@ +# Cavium SOC-specific documentation + +This section contains documentation about coreboot on specific Cavium SOCs. + +## Platforms + +- [CN81xx series](cn81xx/index.md) +- [CN8xxx bootflow](bootflow.md) diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md index ca50dc85fb..04e2b2f2eb 100644 --- a/Documentation/soc/index.md +++ b/Documentation/soc/index.md @@ -4,4 +4,5 @@ This section contains documentation about coreboot on specific SOCs. ## Vendor +- [Cavium](cavium/index.md) - [Intel](intel/index.md) -- cgit v1.2.3