From 8c986ab26358b40863f7404c97e8afbb118789f1 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 18 Jun 2018 13:23:27 +0200 Subject: Documentation: Add cavium SoC and mainboard * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Philipp Deppenwiese --- Documentation/soc/cavium/bootflow.md | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/soc/cavium/bootflow.md (limited to 'Documentation/soc/cavium/bootflow.md') diff --git a/Documentation/soc/cavium/bootflow.md b/Documentation/soc/cavium/bootflow.md new file mode 100644 index 0000000000..70bf865447 --- /dev/null +++ b/Documentation/soc/cavium/bootflow.md @@ -0,0 +1,19 @@ +# Cavium bootflow + +The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller. +It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get +the position of the bootstage in flash. It then loads 192KiB from flash into +L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as +the signature of the bootstage isn't verified. +The **BOOTROM** can do AES decryption for obfuscation or verify the signature +of the bootstage. Both features aren't used and won't be described any further. + +* The typical position of bootstage in flash is at address **0x20000**. +* The entry point in physical DRAM is at address **0x100000**. + +## Layout + +![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow] + +[cavium_bootflow]: cavium_bootflow.png + -- cgit v1.2.3