From 8618cf1edc68121e420d9a82483cc351040fd487 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 10 May 2021 07:32:20 +0300 Subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Werner Zeh Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- Documentation/releases/coreboot-4.14-relnotes.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/releases') diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 6b629f476a..b6c927ee12 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -61,4 +61,19 @@ of the existing Picasso SoC code the common parts of the code were moved to the common AMD SoC code, so that they could be used by the Cezanne code instead of adding another slightly different copy. +### X86 bootblock layout + +The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favor of +dynamically allocating the stage size; the Kconfig is still available +to use as a fixed size and to enforce a maximum for selected chipsets. +Linker sections are now top-aligned for a reduced flash footprint and to +maintain the requirements of near jump from reset vector. + +### ACPI GNVS framework + +SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is +now passed from within SMM_MODULE_LOADER. Allocation and initialisations +for common ACPI GNVS table entries were largely moved to one centralized +implementation. + ### Add significant changes here -- cgit v1.2.3