From 1b95501fad0b94098a1e6c5be637efaf113dcb88 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 5 Nov 2019 08:32:19 +0100 Subject: Documentation: Add some significant 4.11 release notes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Kyösti Mälkki --- Documentation/releases/coreboot-4.11-relnotes.md | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation/releases/coreboot-4.11-relnotes.md') diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 7dd99a3522..38299c13a6 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -40,3 +40,22 @@ removed soon after release. Significant refactoring has bee done to achieve some consistency across platforms and to reduce code duplication. + +### Added VBOOT support to the following platforms: +* intel/gm45 +* intel/nehalem + +### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: +* intel/gm45 +* intel/nehalem +* intel/braswell + +### Other +* Did cleanups around TSC timer +* Improved automatic VR configuration on SKL/KBL +* Filled additional fields in SMBIOS type 4 +* Removed magic value replay from Intel Nehalem/ibexpeak code base +* Added OpenSBI on RISCV platforms +* Did more preparations for Intel TXT support +* Did more preparations for x86_64 stage support +* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb -- cgit v1.2.3