From 0d42a2c421ffbbeaed92496ef5e9fcf241cc98b5 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 11 Jun 2018 19:36:08 +0200 Subject: Documentation: Add SandyBridge NRI feature matrix Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/27093 Reviewed-by: Martin Roth Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../northbridge/intel/sandybridge/index.md | 1 + .../northbridge/intel/sandybridge/nri_features.md | 89 ++++++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 Documentation/northbridge/intel/sandybridge/nri_features.md (limited to 'Documentation/northbridge/intel') diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index 815abcefb5..dcb090aad6 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -5,3 +5,4 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid ## Topics - [Native Ram Initialization](nri.md) +- [RAM initialization feature matrix](nri_features.md) diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md new file mode 100644 index 0000000000..6305e78622 --- /dev/null +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -0,0 +1,89 @@ +# RAM initialization feature matrix + +## Options + +1. Native raminit + * Open Source + * Native Raminit is working for most frequencies on most boards. + * There might be errors to fix. + * Position in romstage doesn't matter. +2. mrc.bin raminit + * Closed Source (aka BLOB) + * No known errors. + * Needs to be placed at fixed offset in romstage. + +## Native raminit implemented features + +```eval_rst ++---------------------------+----------------------+-------------+---------+---------------------+ +| Option | Supported | Implemented | Working | Description | ++===========================+======================+=============+=========+=====================+ +| **Supported channels** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| single and dual channel | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| Up to 4 slots | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| Up to 4 ranks per channel | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **Supported frequencies** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1066 (533MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1600 (800MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1866 (933MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2133 (1066MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1400 (700MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2000 (1000MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2200 (1100MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2400 (1200MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **Supported CAS latencies** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL6 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL7 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL8 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL9 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL10 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL11 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL12 | yes | yes | ? | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL13 | yes | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL14 | yes | yes | ? | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL15 | yes | yes | ? | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **MRC cache (stored timings of last training)** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| S3 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| normal boot | yes | yes | yes | reset on CRC16 diff | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **XMP support** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| XMP Profile 1 | yes | yes | yes | only 1.5 V profiles | ++---------------------------+----------------------+-------------+---------+---------------------+ +| XMP Profile 2 | yes | yes | no | not activated | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **ECC support** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| ECC | yes | no | | | ++---------------------------+----------------------+-------------+---------+---------------------+ +``` -- cgit v1.2.3