From fa1a07bf509bee95a9f4291c9a6fe639ae512d94 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 20 Aug 2018 13:32:57 +0200 Subject: Documentation/northbridge/intel/sandybridge/*: fix typos Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy Bridge". Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/28231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- Documentation/northbridge/intel/sandybridge/nri_registers.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/northbridge/intel/sandybridge/nri_registers.md') diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 601157c464..6249560a6f 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1556,7 +1556,7 @@ Please handle with care ! *Width:* 16 Bit -*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0 +*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0 ```eval_rst +-----------+------------------------------------------------------------------+ @@ -2138,7 +2138,7 @@ Please handle with care ! | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] | +-----------+------------------------------------------------------------------+ | 8 | - 1: 100Mhz reference clock | -| | - 0: 133Mhz reference clock (IvyBridge only) | +| | - 0: 133Mhz reference clock (Ivy Bridge only) | +-----------+------------------------------------------------------------------+ | 31 | PLL busy | +-----------+------------------------------------------------------------------+ -- cgit v1.2.3