From 9747f886db384cb3d1c42dee93f33346dbd25806 Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Sun, 6 Jan 2019 22:04:27 +1300 Subject: Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixed The issue in question was resolved with commit 334be3289d6c ("nb/intel/haswell: Add support for PEG"). Also add a link to the known issues for Haswell, which has some information on PCIe. Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/30689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/mainboard/supermicro/x10slm-f.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/mainboard/supermicro/x10slm-f.md') diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 8d03429ab6..2c2e6a84cd 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -128,10 +128,6 @@ for caveats. ## Known issues -- The x8 PCIe slots do not work, as the Haswell code is missing support. - The code to support it has been written, but it still needs to be - reviewed and merged. - - Broadwell CPUs are not supported. They might work with minimal changes to the code, but this has not been tested. @@ -144,10 +140,14 @@ for caveats. in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS, and hence the OS can do fan control. +```eval_rst +Please also see :doc:`../../northbridge/intel/haswell/known-issues`. +``` + ## Untested - TPM -- PCIe x4 slot (it will almost certainly work) +- PCIe (likely to work, but maybe not at Gen 3 speeds) - BMC (IPMI) functionality - internal serial port - chassis intrusion header -- cgit v1.2.3