From 2452c8414dca45d5e7e3006dc034d523c7ab06b2 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Mon, 25 Mar 2019 16:00:25 +0300 Subject: Doc/mb/asrock/h110m: Fix the links Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/32052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/mainboard/asrock/h110m-dvs.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/mainboard/asrock') diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 614669b154..022768489b 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -5,9 +5,9 @@ This page describes how to run coreboot on the [ASRock H110M-DVS]. ## Required proprietary blobs Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. -Intel company provides [Firmware Support Package (2.0)](../../Documentation/soc/intel/fsp/index.md) +Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md) (intel FSP 2.0) to initialize this generation silicon. Please see this -[document](../../Documentation/soc/intel/code_development_model/code_development_model.md). +[document](../../soc/intel/code_development_model/code_development_model.md). FSP Information: @@ -82,7 +82,7 @@ The main SPI flash can be accessed using [flashrom]. By default, only the BIOS region of the flash is writable. If you wish to change any other region, such as the Management Engine or firmware descriptor, then an external programmer is required (unless you find a clever way around -the flash protection). More information about this [here](../../Documentation/flash_tutorial/index.md). +the flash protection). More information about this [here](../../flash_tutorial/index.md). ### External programming -- cgit v1.2.3