From a8843dee58d15de6860b682975ee01ee61893670 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 5 Jun 2017 12:33:23 +0200 Subject: Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/Intel/Board/board.html | 10 ++--- Documentation/Intel/SoC/soc.html | 82 ++++++++++++++++++------------------ Documentation/Intel/development.html | 8 ++-- 3 files changed, 50 insertions(+), 50 deletions(-) (limited to 'Documentation/Intel') diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index 1b2d323091..489d802709 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -161,20 +161,20 @@
  1. 0x34: - Just after entering - raminit + raminit
  2. 0x36: - Just before displaying the - UPD parameters + UPD parameters for FSP MemoryInit
    3. -
  3. 0x92: POST_FSP_MEMORY_INIT +
  4. 0x92: POST_FSP_MEMORY_INIT - Just before calling FSP - MemoryInit + MemoryInit
  5. 0x37: - Just after returning from FSP - MemoryInit + MemoryInit
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 8f1d75ce64..6f6d6308ab 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -108,11 +108,11 @@ mv build/coreboot.rom.new build/coreboot.rom When the reset vector is successfully invoked, port 0x80 will output the following value:

@@ -154,15 +154,15 @@ mv build/coreboot.rom.new build/coreboot.rom
  • Add the necessary .h files to define the necessary values and structures
  • When successful port 0x80 will output the following values:
      -
    1. 0x01: POST_RESET_VECTOR_CORRECT +
    2. 0x01: POST_RESET_VECTOR_CORRECT - Bootblock successfully executed the - reset vector + reset vector and entered the 16-bit code at - _start + _start
      3. -
    3. 0x10: POST_ENTER_PROTECTED_MODE +
    4. 0x10: POST_ENTER_PROTECTED_MODE - Bootblock executing in - 32-bit mode + 32-bit mode
    5. 0x10 - Verstage/romstage reached 32-bit mode
    @@ -173,26 +173,26 @@ mv build/coreboot.rom.new build/coreboot.rom Build Note: The following files are included into the default bootblock image: