From 7e0078b990b7b498391505fb5c492ff7ed8e54cb Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Sun, 31 Jan 2016 11:48:15 -0800
Subject: Documentation: Add the x86 FSP Binary

Document how to add the FSP binary to the SPI flash image.

TEST=None

Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13442
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 Documentation/Intel/fsp1_1.html | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'Documentation/Intel/fsp1_1.html')

diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html
index e08be830ff..456db802a8 100644
--- a/Documentation/Intel/fsp1_1.html
+++ b/Documentation/Intel/fsp1_1.html
@@ -14,6 +14,7 @@
 </p>
 <ol>
   <li><a href="#RequiredFiles">Required Files</a></li>
+  <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
 </ol>
 
 <p>
@@ -44,6 +45,18 @@
 </ol>
 
 
+<hr>
+<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1>
+<p>
+  Add the FSP binary to the coreboot flash image using the following command:
+</p>
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b &lt;base address&gt; -f fsp.bin</code></pre>
+<p>
+  This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
+  FSP code for TempRamInit may be executed in place.
+</p>
+
+
 <hr>
 <p>Modified: 31 January 2016</p>
   </body>
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