From 66decf16446eeb8d3b2da93d0b0086a583bc17bf Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Thu, 4 Feb 2016 11:21:33 -0800
Subject: Documentation: x86 Enable Serial Output

Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 Documentation/Intel/fsp1_1.html | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'Documentation/Intel/fsp1_1.html')

diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html
index 456db802a8..0727e7ba20 100644
--- a/Documentation/Intel/fsp1_1.html
+++ b/Documentation/Intel/fsp1_1.html
@@ -15,6 +15,7 @@
 <ol>
   <li><a href="#RequiredFiles">Required Files</a></li>
   <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
+  <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
 </ol>
 
 <p>
@@ -57,6 +58,19 @@
 </p>
 
 
+<hr>
+<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1>
+<p>
+  Set the following Kconfig values:
+</p>
+<ul>
+  <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
+  <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
+  <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
+  <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
+</ul>
+
+
 <hr>
 <p>Modified: 31 January 2016</p>
   </body>
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