From fcf776fd02d60ab01b885ce48beae929098d6aad Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 4 Feb 2016 11:23:36 -0800 Subject: Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/development.html | 58 ++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'Documentation/Intel/development.html') diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index b90fa96567..0cd2bd59b7 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -82,6 +82,18 @@
  • Enable coreboot/FSP debugging
    • +
  • Determine the Previous Sleep State
    • +
  • Enable DRAM: +
      +
    1. Implement the SoC + MemoryInit + Support +
      2. +
    2. Implement the board support to read the + Memory Timing Data +
      3. +
    +
    • @@ -124,6 +136,32 @@ Where Testing + + DRAM + + Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/spd.c
    + UPD Setup: +
      +
    • src/soc<Vendor>//<Chip Family>/romstage/romstage.c
      • +
    • src/mainboard/<Vendor>/<Board>/romstage.c
      • +
    + FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/raminit.c + + Select the following Kconfig values +
      +
    • DISPLAY_HOBS
      • +
    • DISPLAY_UPD_DATA
      • +
    + Testing successful if: +
      +
    • MemoryInit UPD values are correct
      • +
    • MemoryInit returns 0 (success) and
      • +
    • The the message "ERROR - coreboot's requirements not met by FSP binary!" + is not displayed +
      • +
    + + Serial Port @@ -150,6 +188,26 @@ is displayed
    + + MemoryInit + SoC support
    + Board support
    + + Select the following Kconfig values +
      +
    • DISPLAY_HOBS
      • +
    • DISPLAY_UPD_DATA
      • +
    + Testing successful if: +
      +
    • MemoryInit UPD values are correct
      • +
    • MemoryInit returns 0 (success) and
      • +
    • The the message "ERROR - coreboot's requirements not met by FSP binary!" + is not displayed +
      • +
    + + -- cgit v1.2.3