From e9a6d1a813f61b505f9463160c27992419cb9056 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Sun, 31 Jan 2016 11:28:06 -0800
Subject: Documentation: x86 shadow ROM disable

Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 Documentation/Intel/development.html | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'Documentation/Intel/development.html')

diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 7b82321266..a36acaa56a 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -94,6 +94,9 @@
       </li>
     </ol>
   </li>
+  <li>Disable the
+    <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
+  </li>
   <li>
     Implement the .init routine for the
     <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
@@ -198,6 +201,13 @@
       for the PCI devices on the bus.
     </td>
   </tr>
+  <tr>
+    <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
+    <td>
+      Disable: src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
+    </td>
+    <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
+  </tr>
 
 
   <tr bgcolor="#c0ffc0">
@@ -346,6 +356,6 @@
 
 
 <hr>
-<p>Modified: 24 February 2016</p>
+<p>Modified: 4 March 2016</p>
   </body>
 </html>
\ No newline at end of file
-- 
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