From bf08da27d56f12e9176fc419f39b4951cd46a8f2 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Sat, 20 Feb 2016 17:48:35 -0800
Subject: Documentation/Intel: Add minimal APCI and TempRamExit documentation

Update the documentation to add the minimal ACPI support.  Also add
TempRamExit entry to the FSP features table.

TEST=None

Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 Documentation/Intel/development.html | 43 +++++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

(limited to 'Documentation/Intel/development.html')

diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index a3136d19d1..74a476fdc0 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -116,6 +116,21 @@
 
 
 
+<h2>Add coreboot Features</h2>
+<p>
+  Most of the coreboot development gets done in this phase.  Implementation tasks in this
+  phase are easily done in parallel.
+</p>
+<ul>
+  <li>Payload and OS Features:
+    <ul>
+      <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
+    </ul>
+  </li>
+</ul>
+
+
+
 <hr>
 <table border="1">
   <tr bgcolor="#c0ffc0">
@@ -228,6 +243,20 @@
   </tr>
 
 
+  <tr bgcolor="#c0ffc0">
+    <th>Payload</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>ACPI Tables</td>
+    <td>
+      SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
+    </td>
+    <td>Verified by payload or OS</td>
+  </tr>
+
+
   <tr bgcolor="#c0ffc0">
     <th>FSP</th>
     <th>Where</th>
@@ -264,6 +293,18 @@
       </ul>
     </td>
   </tr>
+  <tr>
+    <td>TempRamExit</td>
+    <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
+    <td>Post code 0x91
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
+      is displayed before calling TempRamExit by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
+      CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
+      Post code 0x39 is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
+    </td>
+  </tr>
   <tr>
     <td>SiliconInit</td>
     <td>
@@ -294,6 +335,6 @@
 
 
 <hr>
-<p>Modified: 15 February 2016</p>
+<p>Modified: 20 February 2016</p>
   </body>
 </html>
\ No newline at end of file
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