From a8843dee58d15de6860b682975ee01ee61893670 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 5 Jun 2017 12:33:23 +0200 Subject: Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/Intel/development.html | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/Intel/development.html') diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index a2ba2781e0..24b2fa9261 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -170,7 +170,7 @@ after_raminit.S
FindFSP: POST code 0x90 - (POST_FSP_TEMP_RAM_INIT) + (POST_FSP_TEMP_RAM_INIT) is displayed
Enable: POST code 0x2A @@ -303,7 +303,7 @@ TempRamInit FSP TempRamInit FSP binary found: POST code 0x90 - (POST_FSP_TEMP_RAM_INIT) + (POST_FSP_TEMP_RAM_INIT) is displayed
TempRamInit successful: POST code 0x2A @@ -332,7 +332,7 @@ TempRamExit - src/drivers/intel/fsp1_1/after_raminit.S + src/drivers/intel/fsp1_1/after_raminit.S Post code 0x91 (POST_FSP_TEMP_RAM_EXIT) is displayed before calling TempRamExit by @@ -354,7 +354,7 @@ FspNotify The code which calls FspNotify is located in - src/drivers/intel/fsp1_1/fsp_util.c. + src/drivers/intel/fsp1_1/fsp_util.c. The fsp_notify_boot_state_callback routine is called three times as specified by the BOOT_STATE_INIT_ENTRY macros below the routine. -- cgit v1.2.3