From a4d81809137b8b53903303b201c2d1bfbc615143 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 31 Jan 2016 12:19:13 -0800 Subject: Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/development.html | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/Intel/development.html') diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index a36acaa56a..a2ba2781e0 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -97,6 +97,7 @@
  • Disable the Shadow ROM
    • +
  • Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration
  • Implement the .init routine for the chip operations @@ -115,6 +116,7 @@ Implement the memory map
    • +
  • coreboot should now attempt to load the payload
    • @@ -184,6 +186,20 @@ coreboot displays the memory map correctly during the BS_WRITE_TABLES state + + MTRRs + + Set values: src/drivers/intel/fsp1_1/stack.c/setup_stack_and_mtrrs
    + Load values: src/drivers/intel/fsp1_1/after_raminit.S + + Set: Post code 0x91 + (POST_FSP_TEMP_RAM_EXIT) + is displayed by + after_raminit.S
    + Load: Post code 0x3C is displayed by + after_raminit.S
    + and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions + PCI Device Support Implement a PCI device driver -- cgit v1.2.3