From e9a6d1a813f61b505f9463160c27992419cb9056 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Sun, 31 Jan 2016 11:28:06 -0800
Subject: Documentation: x86 shadow ROM disable

Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 Documentation/Intel/SoC/soc.html | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'Documentation/Intel/SoC')

diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 2380cdf61e..8f1d75ce64 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -24,6 +24,7 @@
       <li>Enable <a href="#SerialOutput">Serial Output"</a></li>
       <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
       <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
+      <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li>
     </ol>
   </li>
   <li><a href="#Ramstage">Ramstage</a>
@@ -389,6 +390,17 @@ Use the following steps to debug the call to TempRamInit:
 </ol>
 
 
+<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2>
+<p>
+  A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff.
+  This shadow needs to be disabled to allow RAM to properly respond to
+  this address range.
+</p>
+<ol>
+  <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li>
+</ol>
+
+
 <hr>
 <h1><a name="Ramstage">Ramstage</a></h1>
 
@@ -717,6 +729,6 @@ Use the following steps to debug the call to TempRamInit:
 </table>
 
 <hr>
-<p>Modified: 28 February 2016</p>
+<p>Modified: 4 March 2016</p>
   </body>
 </html>
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