From fcf776fd02d60ab01b885ce48beae929098d6aad Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 4 Feb 2016 11:23:36 -0800 Subject: Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/SoC/soc.html | 53 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'Documentation/Intel/SoC/soc.html') diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 0b0615d049..b5daac8fb5 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -22,6 +22,8 @@
  • Romstage
    1. Enable Serial Output"
      2. +
    2. Get the Previous Sleep State
      3. +
    3. Add the MemoryInit Support
    • @@ -328,6 +330,57 @@ Use the following steps to debug the call to TempRamInit: +

    Determine Previous Sleep State

    +

    + The following steps implement the code to get the previous sleep state: +

    +
      +
    1. Implement the fill_power_state routine which determines the previous sleep state
      2. +
    2. Debug the result until port 0x80 outputs +
        +
      1. 0x32: + - Just after entering + romstage_common +
        2. +
      2. 0x33 - Just after calling + soc_pre_ram_init +
        3. +
      3. 0x34: + - Just after entering + raminit +
        4. +
      +
    + + +

    MemoryInit Support

    +

    + The following steps implement the code to support the FSP MemoryInit call: +

    +
      +
    1. Add the chip.h header file to define the UPD values which get passed + to MemoryInit. Skip the values containing SPD addresses and DRAM + configuration data which is determined by the board. +

      + Build Note: The src/mainboard/<Vendor>/<Board>/devicetree.cb + file specifies the default values for these parameters. The build + process creates the static.c module which contains the config data + structure containing these values. +

      +
      2. +
    2. Edit romstage/romstage.c +
        +
      1. Implement the romstage/romstage.c/soc_memory_init_params routine to + copy the values from the config structure into the UPD structure +
        2. +
      2. Implement the soc_display_memory_init_params routine to display + the updated UPD parameters by calling fsp_display_upd_value +
        3. +
      +
      3. +
    + +

    Modified: 31 January 2016

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