From 7719d50352272e27528f99e60df1c861300e14a9 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sun, 15 Apr 2018 20:33:50 +0200 Subject: Documentation/Intel: Adjust heading levels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- Documentation/Intel/SoC/soc.html | 52 ++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 26 deletions(-) (limited to 'Documentation/Intel/SoC/soc.html') diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 147b0a1a8e..d91166fd2c 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -39,7 +39,7 @@
-

Required Files

+

Required Files

Create the directory as src/soc/<Vendor>/<Chip Family>.

@@ -69,13 +69,13 @@
-

Start Booting

+

Start Booting

Some SoC parts require additional firmware components in the flash. This section describes how to add those pieces.

-

Intel Firmware Descriptor

+

Intel Firmware Descriptor

The Intel Firmware Descriptor (IFD) is located at the base of the flash part. The following command overwrites the base of the flash image with the Intel @@ -84,7 +84,7 @@ 

dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1
-

Management Engine Binary

+

Management Engine Binary

Some SoC parts contain and require that the Management Engine (ME) be running before it is possible to bring the x86 processor out of reset. A binary file @@ -96,14 +96,14 @@ mv build/coreboot.rom.new build/coreboot.rom -

Early Debug

+

Early Debug

Early debugging between the reset vector and the time the serial port is enabled is most easily done by writing values to port 0x80.

-

Success

+

Success

When the reset vector is successfully invoked, port 0x80 will output the following value:

@@ -118,7 +118,7 @@ mv build/coreboot.rom.new build/coreboot.rom
-

Bootblock

+

Bootblock

Implement the bootblock using the following steps:

@@ -213,7 +213,7 @@ mv build/coreboot.rom.new build/coreboot.rom
-

TempRamInit

+

TempRamInit

Enable the call to TempRamInit in two stages:

@@ -223,7 +223,7 @@ mv build/coreboot.rom.new build/coreboot.rom -

Find FSP Binary

+

Find FSP Binary

Use the following steps to locate the FSP binary:

@@ -267,7 +267,7 @@ Use the following steps to locate the FSP binary: -

Calling TempRamInit

+

Calling TempRamInit

Use the following steps to debug the call to TempRamInit:

@@ -301,9 +301,9 @@ Use the following steps to debug the call to TempRamInit:
-

Romstage

+

Romstage

-

Serial Output

+

Serial Output

The following steps add the serial output support for romstage:

@@ -339,7 +339,7 @@ Use the following steps to debug the call to TempRamInit: -

Determine Previous Sleep State

+

Determine Previous Sleep State

The following steps implement the code to get the previous sleep state:

@@ -362,7 +362,7 @@ Use the following steps to debug the call to TempRamInit: -

MemoryInit Support

+

MemoryInit Support

The following steps implement the code to support the FSP MemoryInit call:

@@ -390,7 +390,7 @@ Use the following steps to debug the call to TempRamInit: -

Disable Shadow ROM

+

Disable Shadow ROM

A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. This shadow needs to be disabled to allow RAM to properly respond to @@ -402,9 +402,9 @@ Use the following steps to debug the call to TempRamInit:

-

Ramstage

+

Ramstage

-

Start Device Tree Processing

+

Start Device Tree Processing

The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the execution during ramstage. This file is processed by the util/sconfig utility @@ -417,7 +417,7 @@ Use the following steps to debug the call to TempRamInit: state of the state machine.

-

Chip Operations

+

Chip Operations

Kick-starting the ramstage state machine requires creating the operation table for the chip listed in devicetree.cb: @@ -437,7 +437,7 @@ Use the following steps to debug the call to TempRamInit:

  • Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage
    • -

    Domain Operations

    +

    Domain Operations

    coreboot uses the domain operation table to initiate operations on all of the devices in the domain. By default coreboot enables all PCI devices which it @@ -482,7 +482,7 @@ Use the following steps to debug the call to TempRamInit: -

    PCI Device Drivers

    +

    PCI Device Drivers

    PCI device drivers consist of a ".c" file which contains a "pci_driver" data structure at the end of the file with the attribute tag "__pci_driver". This @@ -509,7 +509,7 @@ Use the following steps to debug the call to TempRamInit: -

    Subsystem IDs

    +

    Subsystem IDs

    PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device driver may use the common mechanism to assign subsystem IDs by adding @@ -534,7 +534,7 @@ Use the following steps to debug the call to TempRamInit: -

    Set up the Memory Map

    +

    Set up the Memory Map

    The memory map is built by the various PCI device drivers during the BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically @@ -571,12 +571,12 @@ Use the following steps to debug the call to TempRamInit:

    -

    ACPI Tables

    +

    ACPI Tables

    One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg.

    -

    FADT

    +

    FADT

    The EDK2 module CorebootModulePkg/Library/CbParseLib/CbParseLib.c @@ -679,7 +679,7 @@ Use the following steps to debug the call to TempRamInit:

    -

    Legacy Hardware

    +

    Legacy Hardware

    One of the payloads that needs legacy hardare is the EDK2 CorebootPayloadPkg.

    @@ -731,4 +731,4 @@ Use the following steps to debug the call to TempRamInit:

    Modified: 4 March 2016

    - \ No newline at end of file + -- cgit v1.2.3