From 8ee93ae26786c11f5169aedceb5b2670ff53568a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 9 Apr 2018 13:05:29 +0200 Subject: Documentation: Fix a bunch of typos MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/25571 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Patrick Georgi --- Documentation/Intel/NativeRaminit/SandyBridge_registers.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/Intel/NativeRaminit/SandyBridge_registers.md') diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md index 2dce11bcc8..c96189088c 100644 --- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md +++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md @@ -966,7 +966,7 @@ Please handle with care ! *Width:* 24 Bit -*Desc:* TC_DBP - Timming of DDR - Bin Parameter Register, Channel 0 +*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0 |Bit| Description | |---|-------------| -- cgit v1.2.3