From fcf776fd02d60ab01b885ce48beae929098d6aad Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 4 Feb 2016 11:23:36 -0800 Subject: Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/Board/board.html | 79 ++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'Documentation/Intel/Board') diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index d50ff4e74f..47d329515d 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -15,6 +15,7 @@
  1. Required Files
  2. Enable Serial Output
    3. +
  3. Load the Memory Timing Data
@@ -101,6 +102,84 @@ +
+

Memory Timing Data

+

+ Memory timing data is located in the flash. This data is in the format of + serial presence detect + (SPD) data. + Use the following steps to load the SPD data: +

+
    +
  1. Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the + display of the SPD data being passed to MemoryInit +
    2. +
  2. Create an "spd" subdirectory
    3. +
  3. Create an spd/spd.c file for the SPD implementation +
      +
    1. Implement the mainboard_fill_spd_data routine +
        +
      1. Read the SPD data either from the spd.bin file or using I2C or SMBUS
        2. +
      2. Fill in the pei_data structure with SPD data for each of the DIMMs
        3. +
      3. Set the DIMM channel configuration
        4. +
      +
      2. +
    +
    4. +
  4. Add an .spd.hex file containing the memory timing data to the spd subdirectory
    5. +
  5. Create spd/Makefile.inc +
      +
    1. Add spd.c to romstage
      2. +
    2. Add the .spd.hex file to SPD_SOURCES
      3. +
    +
    6. +
  6. Edit Makefile.inc to add the spd subdirectory
    7. +
  7. Edit romstage.c +
      +
    1. Call mainboard_fill_spd_data
      2. +
    2. Add mainboard_memory_init_params to copy the SPD and DRAM + configuration data from the pei_data structure into the UPDs + for MemoryInit +
      3. +
    +
    8. +
  8. Edit devicetree.cb +
      +
    1. Include the UPD parameters for MemoryInit except for: +
        +
      • Address of SPD data
        • +
      • DRAM configuration set above
        • +
      +
      2. +
    +
    9. +
  9. A working FSP + MemoryInit + routine is required to complete debugging
    10. +
  10. Debug the result until port 0x80 outputs +
      +
    1. 0x34: + - Just after entering + raminit +
      2. +
    2. 0x36: + - Just before displaying the + UPD parameters + for FSP MemoryInit +
      3. +
    3. 0x92: POST_FSP_MEMORY_INIT + - Just before calling FSP + MemoryInit +
      4. +
    4. 0x37: + - Just after returning from FSP + MemoryInit +
      5. +
    +
    11. +
  11. Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called
    12. +
+

Modified: 31 January 2016

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