From ffe4aededf4b62db3da3a61a99a3ff3d447f61e2 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 6 Dec 2018 22:53:44 -0800 Subject: mb/google/sarien: Enable LAN clock source usage FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 +- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93e0af978b..fccec9f3b6 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -80,7 +80,7 @@ chip soc/intel/cannonlake # PCIe port 9 for LAN register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[0]" = "0" # PCIe port 10 for M.2 2230 WLAN diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d25e725545..49200ad511 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -85,7 +85,7 @@ chip soc/intel/cannonlake # PCIe port 9 for LAN register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[3]" = "3" # PCIe port 10 for M.2 2230 WLAN -- cgit v1.2.3