From fefce185335232aade9e512a1cbe94da27578768 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Thu, 19 Nov 2015 16:30:18 +0530 Subject: intel/kunimitsu: Enable FspSkipMpInit token MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310192 Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a Signed-off-by: Patrick Georgi Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45 Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516 Original-Signed-off-by: Barnali Sarkar Original-Signed-off-by: Rizwan Qureshi Original-Reviewed-on: https://chromium-review.googlesource.com/312926 Original-Commit-Ready: Preetham Chandrian Original-Tested-by: Preetham Chandrian Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/12992 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/kunimitsu/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index e75959e075..75bb7c40f8 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -126,6 +126,8 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" + register "FspSkipMpInit" = "1" + # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" register "PcieRpEnable[4]" = "1" -- cgit v1.2.3