From feddd37297d2157504540aa861e86e7e2aeba782 Mon Sep 17 00:00:00 2001
From: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Date: Wed, 20 Nov 2024 10:40:57 +0800
Subject: soc/mediatek: Rename dpm to dpm_v1

MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we need implement a new DPM loader (said version 2) to run
the blob. Considering the version iteration, rename the original dpm to
dpm_v1.

TEST=Build pass.
BUG=b:317009620

Change-Id: I07afb8f5c23e96aad3c6cb0887cb7efd16ebf296
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/asurada/mainboard.c     |  2 +-
 src/mainboard/google/cherry/mainboard.c      |  2 +-
 src/soc/mediatek/common/dpm.c                | 58 ----------------------------
 src/soc/mediatek/common/dpm_4ch.c            |  2 +-
 src/soc/mediatek/common/dpm_v1.c             | 58 ++++++++++++++++++++++++++++
 src/soc/mediatek/common/include/soc/dpm.h    | 56 ---------------------------
 src/soc/mediatek/common/include/soc/dpm_v1.h | 56 +++++++++++++++++++++++++++
 src/soc/mediatek/mt8188/Makefile.mk          |  2 +-
 src/soc/mediatek/mt8188/soc.c                |  2 +-
 src/soc/mediatek/mt8192/Makefile.mk          |  2 +-
 src/soc/mediatek/mt8195/Makefile.mk          |  2 +-
 11 files changed, 121 insertions(+), 121 deletions(-)
 delete mode 100644 src/soc/mediatek/common/dpm.c
 create mode 100644 src/soc/mediatek/common/dpm_v1.c
 delete mode 100644 src/soc/mediatek/common/include/soc/dpm.h
 create mode 100644 src/soc/mediatek/common/include/soc/dpm_v1.h

diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index 2da9719a19..358717b690 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -11,7 +11,7 @@
 #include <gpio.h>
 #include <soc/bl31.h>
 #include <soc/ddp.h>
-#include <soc/dpm.h>
+#include <soc/dpm_v1.h>
 #include <soc/dsi.h>
 #include <soc/gpio_common.h>
 #include <soc/i2c.h>
diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c
index 19638c97f6..16eabbac37 100644
--- a/src/mainboard/google/cherry/mainboard.c
+++ b/src/mainboard/google/cherry/mainboard.c
@@ -9,7 +9,7 @@
 #include <gpio.h>
 #include <soc/bl31.h>
 #include <soc/display.h>
-#include <soc/dpm.h>
+#include <soc/dpm_v1.h>
 #include <soc/i2c.h>
 #include <soc/msdc.h>
 #include <soc/mtcmos.h>
diff --git a/src/soc/mediatek/common/dpm.c b/src/soc/mediatek/common/dpm.c
deleted file mode 100644
index 0bcf409399..0000000000
--- a/src/soc/mediatek/common/dpm.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <soc/dpm.h>
-#include <soc/mcu_common.h>
-#include <soc/symbols.h>
-
-static struct mtk_mcu dpm_mcu[] = {
-	{
-		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
-		.run_address = (void *)DPM_DM_SRAM_BASE,
-	},
-	{
-		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
-		.run_address = (void *)DPM_PM_SRAM_BASE,
-		.priv = mtk_dpm,
-		.reset = dpm_reset,
-	},
-};
-
-void dpm_reset(struct mtk_mcu *mcu)
-{
-	struct dpm_regs *dpm = mcu->priv;
-
-	/* write bootargs */
-	write32(&dpm->twam_window_len, 0x0);
-	write32(&dpm->twam_mon_type, 0x0);
-
-	/* free RST */
-	setbits32(&dpm->sw_rstn, DPM_SW_RSTN_RESET);
-}
-
-int dpm_init(void)
-{
-	int i;
-	struct mtk_mcu *dpm;
-
-	if (CONFIG(DPM_FOUR_CHANNEL))
-		if (dpm_4ch_init())
-			return -1;
-
-	/* config DPM SRAM layout */
-	clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1);
-
-	for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) {
-		dpm = &dpm_mcu[i];
-		dpm->load_buffer = _dram_dma;
-		dpm->buffer_size = REGION_SIZE(dram_dma);
-		if (mtk_init_mcu(dpm))
-			return -1;
-	}
-
-	if (CONFIG(DPM_FOUR_CHANNEL))
-		if (dpm_4ch_para_setting())
-			return -1;
-
-	return 0;
-}
diff --git a/src/soc/mediatek/common/dpm_4ch.c b/src/soc/mediatek/common/dpm_4ch.c
index f13337d8b7..6b15411300 100644
--- a/src/soc/mediatek/common/dpm_4ch.c
+++ b/src/soc/mediatek/common/dpm_4ch.c
@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/mmio.h>
-#include <soc/dpm.h>
+#include <soc/dpm_v1.h>
 #include <soc/dramc_soc.h>
 #include <soc/spm.h>
 #include <soc/symbols.h>
diff --git a/src/soc/mediatek/common/dpm_v1.c b/src/soc/mediatek/common/dpm_v1.c
new file mode 100644
index 0000000000..4691b35569
--- /dev/null
+++ b/src/soc/mediatek/common/dpm_v1.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/dpm_v1.h>
+#include <soc/mcu_common.h>
+#include <soc/symbols.h>
+
+static struct mtk_mcu dpm_mcu[] = {
+	{
+		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
+		.run_address = (void *)DPM_DM_SRAM_BASE,
+	},
+	{
+		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
+		.run_address = (void *)DPM_PM_SRAM_BASE,
+		.priv = mtk_dpm,
+		.reset = dpm_reset,
+	},
+};
+
+void dpm_reset(struct mtk_mcu *mcu)
+{
+	struct dpm_regs *dpm = mcu->priv;
+
+	/* write bootargs */
+	write32(&dpm->twam_window_len, 0x0);
+	write32(&dpm->twam_mon_type, 0x0);
+
+	/* free RST */
+	setbits32(&dpm->sw_rstn, DPM_SW_RSTN_RESET);
+}
+
+int dpm_init(void)
+{
+	int i;
+	struct mtk_mcu *dpm;
+
+	if (CONFIG(DPM_FOUR_CHANNEL))
+		if (dpm_4ch_init())
+			return -1;
+
+	/* config DPM SRAM layout */
+	clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1);
+
+	for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) {
+		dpm = &dpm_mcu[i];
+		dpm->load_buffer = _dram_dma;
+		dpm->buffer_size = REGION_SIZE(dram_dma);
+		if (mtk_init_mcu(dpm))
+			return -1;
+	}
+
+	if (CONFIG(DPM_FOUR_CHANNEL))
+		if (dpm_4ch_para_setting())
+			return -1;
+
+	return 0;
+}
diff --git a/src/soc/mediatek/common/include/soc/dpm.h b/src/soc/mediatek/common/include/soc/dpm.h
deleted file mode 100644
index e72b6a1f3d..0000000000
--- a/src/soc/mediatek/common/include/soc/dpm.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_COMMON_DPM_H__
-#define __SOC_MEDIATEK_COMMON_DPM_H__
-
-#include <soc/addressmap.h>
-#include <soc/mcu_common.h>
-#include <types.h>
-
-struct dpm_regs {
-	u32 sw_rstn;
-	u32 rsvd_0[3072];
-	u32 mclk_div;
-	u32 rsvd_1[3071];
-	u32 twam_window_len;
-	u32 twam_mon_type;
-	u32 rsvd_2[1022];
-	u32 low_power_cfg_0;
-	u32 low_power_cfg_1;
-	u32 rsvd_3[1];
-	u32 fsm_out_ctrl_0;
-	u32 rsvd_4[8];
-	u32 fsm_cfg_1;
-	u32 low_power_cfg_3;
-	u32 dfd_dbug_0;
-	u32 rsvd_5[28];
-	u32 status_4;
-};
-
-check_member(dpm_regs, mclk_div, 0x3004);
-check_member(dpm_regs, twam_window_len, 0x6004);
-check_member(dpm_regs, low_power_cfg_0, 0x7004);
-check_member(dpm_regs, low_power_cfg_1, 0x7008);
-check_member(dpm_regs, fsm_out_ctrl_0, 0x7010);
-check_member(dpm_regs, fsm_cfg_1, 0x7034);
-check_member(dpm_regs, low_power_cfg_3, 0x7038);
-check_member(dpm_regs, dfd_dbug_0, 0x703C);
-check_member(dpm_regs, status_4, 0x70B0);
-
-#define DPM_SW_RSTN_RESET	BIT(0)
-#define DPM_MEM_RATIO_OFFSET	28
-#define DPM_MEM_RATIO_MASK	(0x3 << DPM_MEM_RATIO_OFFSET)
-#define DPM_MEM_RATIO_CFG1	(1 << DPM_MEM_RATIO_OFFSET)
-#define DRAMC_MCU_SRAM_ISOINT_B_LSB		BIT(1)
-#define DRAMC_MCU2_SRAM_ISOINT_B_LSB		BIT(1)
-#define DRAMC_MCU_SRAM_SLEEP_B_LSB		BIT(4)
-#define DRAMC_MCU2_SRAM_SLEEP_B_LSB		BIT(4)
-
-static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE;
-
-void dpm_reset(struct mtk_mcu *mcu);
-int dpm_init(void);
-int dpm_4ch_para_setting(void);
-int dpm_4ch_init(void);
-
-#endif  /* __SOC_MEDIATEK_COMMON_DPM_H__ */
diff --git a/src/soc/mediatek/common/include/soc/dpm_v1.h b/src/soc/mediatek/common/include/soc/dpm_v1.h
new file mode 100644
index 0000000000..65623a2671
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dpm_v1.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_DPM_V1_H__
+#define __SOC_MEDIATEK_COMMON_DPM_V1_H__
+
+#include <soc/addressmap.h>
+#include <soc/mcu_common.h>
+#include <types.h>
+
+struct dpm_regs {
+	u32 sw_rstn;
+	u32 rsvd_0[3072];
+	u32 mclk_div;
+	u32 rsvd_1[3071];
+	u32 twam_window_len;
+	u32 twam_mon_type;
+	u32 rsvd_2[1022];
+	u32 low_power_cfg_0;
+	u32 low_power_cfg_1;
+	u32 rsvd_3[1];
+	u32 fsm_out_ctrl_0;
+	u32 rsvd_4[8];
+	u32 fsm_cfg_1;
+	u32 low_power_cfg_3;
+	u32 dfd_dbug_0;
+	u32 rsvd_5[28];
+	u32 status_4;
+};
+
+check_member(dpm_regs, mclk_div, 0x3004);
+check_member(dpm_regs, twam_window_len, 0x6004);
+check_member(dpm_regs, low_power_cfg_0, 0x7004);
+check_member(dpm_regs, low_power_cfg_1, 0x7008);
+check_member(dpm_regs, fsm_out_ctrl_0, 0x7010);
+check_member(dpm_regs, fsm_cfg_1, 0x7034);
+check_member(dpm_regs, low_power_cfg_3, 0x7038);
+check_member(dpm_regs, dfd_dbug_0, 0x703C);
+check_member(dpm_regs, status_4, 0x70B0);
+
+#define DPM_SW_RSTN_RESET	BIT(0)
+#define DPM_MEM_RATIO_OFFSET	28
+#define DPM_MEM_RATIO_MASK	(0x3 << DPM_MEM_RATIO_OFFSET)
+#define DPM_MEM_RATIO_CFG1	(1 << DPM_MEM_RATIO_OFFSET)
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB		BIT(1)
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB		BIT(1)
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB		BIT(4)
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB		BIT(4)
+
+static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE;
+
+void dpm_reset(struct mtk_mcu *mcu);
+int dpm_init(void);
+int dpm_4ch_para_setting(void);
+int dpm_4ch_init(void);
+
+#endif  /* __SOC_MEDIATEK_COMMON_DPM_V1_H__ */
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 8d1b783784..e9e70880bd 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -40,7 +40,7 @@ ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
-ramstage-y += ../common/dpm.c
+ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
 ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/emi.c
diff --git a/src/soc/mediatek/mt8188/soc.c b/src/soc/mediatek/mt8188/soc.c
index f2911aec10..665f391ec6 100644
--- a/src/soc/mediatek/mt8188/soc.c
+++ b/src/soc/mediatek/mt8188/soc.c
@@ -6,7 +6,7 @@
 #include <soc/cpu_input_gating.h>
 #include <soc/devapc.h>
 #include <soc/dfd.h>
-#include <soc/dpm.h>
+#include <soc/dpm_v1.h>
 #include <soc/emi.h>
 #include <soc/mcupm.h>
 #include <soc/mmu_operations.h>
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index 0847439df3..8b409baa10 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -38,7 +38,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += devapc.c
 ramstage-y += ../common/dfd.c
-ramstage-y += ../common/dpm.c
+ramstage-y += ../common/dpm_v1.c
 ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index 22f163b2d4..3ece4adf1f 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -48,7 +48,7 @@ ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
-ramstage-y += ../common/dpm.c
+ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
 ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
 ramstage-y += emi.c
-- 
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