From fd19075045b6834cab2b01e04e6192e6ca71f429 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 15 Sep 2020 12:38:17 +0200 Subject: nb/intel/x4x: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45421 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/hostbridge_regs.h | 40 ----------------------- src/northbridge/intel/x4x/registers/host_bridge.h | 40 +++++++++++++++++++++++ src/northbridge/intel/x4x/x4x.h | 2 +- 3 files changed, 41 insertions(+), 41 deletions(-) delete mode 100644 src/northbridge/intel/x4x/hostbridge_regs.h create mode 100644 src/northbridge/intel/x4x/registers/host_bridge.h diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/hostbridge_regs.h deleted file mode 100644 index 00b496dca8..0000000000 --- a/src/northbridge/intel/x4x/hostbridge_regs.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __X4X_HOSTBRIDGE_REGS_H__ -#define __X4X_HOSTBRIDGE_REGS_H__ - -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define D0EN (1 << 0) -#define D1EN (1 << 1) -#define IGD0EN (1 << 3) -#define IGD1EN (1 << 4) -#define D3F0EN (1 << 6) -#define D3F1EN (1 << 7) -#define D3F2EN (1 << 8) -#define D3F3EN (1 << 9) -#define PEG1EN (1 << 13) -#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_GBSM 0xa4 -#define D0F0_BGSM 0xa8 -#define D0F0_TSEG 0xac -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 - -#endif /* __X4X_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/x4x/registers/host_bridge.h b/src/northbridge/intel/x4x/registers/host_bridge.h new file mode 100644 index 0000000000..f09240416f --- /dev/null +++ b/src/northbridge/intel/x4x/registers/host_bridge.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_HOSTBRIDGE_H__ +#define __X4X_REGISTERS_HOSTBRIDGE_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0EN (1 << 0) +#define D1EN (1 << 1) +#define IGD0EN (1 << 3) +#define IGD1EN (1 << 4) +#define D3F0EN (1 << 6) +#define D3F1EN (1 << 7) +#define D3F2EN (1 << 8) +#define D3F3EN (1 << 9) +#define PEG1EN (1 << 13) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +#endif /* __X4X_REGISTERS_HOSTBRIDGE_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index c62428705f..25345756e0 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -11,7 +11,7 @@ */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* * D1:F0 PEG -- cgit v1.2.3