From fc3741f379f972d9d7d962fa4e62cec7a01f5e86 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Thu, 26 May 2016 17:12:17 -0700
Subject: Add Board Checklist Support

Build the <board>_checklist.html file which contains a checklist table
for each stage of coreboot.  This processing builds a set of implemented
(done) routines which are marked green in the table.  The remaining
required routines (work-to-do) are marked red in the table and the
optional routines are marked yellow in the table.  The table heading
for each stage contains a completion percentage in terms of count of
routines (done .vs. required).

Add some Kconfig values:
*  CREATE_BOARD_CHECKLIST - When selected creates the checklist file
*  MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the
   Documenation directory
*  CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files:
   *  <stage>_complete.dat - Lists all of the weak routines
   *  <stage>_optional.dat - Lists weak routines which may be optionally
      implemented

TEST=Build with Galileo Gen2.

Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 Makefile.inc                                       |   1 +
 src/Kconfig                                        |  30 +++
 src/drivers/intel/fsp1_1/Kconfig                   |   4 +
 .../fsp/fsp1_1/checklist/bootblock_complete.dat    |  77 ++++++
 .../fsp/fsp1_1/checklist/ramstage_complete.dat     |  53 +++++
 .../fsp/fsp1_1/checklist/ramstage_optional.dat     |  46 ++++
 .../fsp/fsp1_1/checklist/romstage_complete.dat     |  54 +++++
 .../fsp/fsp1_1/checklist/romstage_optional.dat     |  34 +++
 .../fsp/fsp1_1/checklist/verstage_complete.dat     |  35 +++
 .../fsp/fsp1_1/checklist/verstage_optional.dat     |  22 ++
 util/checklist/Makefile.inc                        | 260 +++++++++++++++++++++
 11 files changed, 616 insertions(+)
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
 create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
 create mode 100644 util/checklist/Makefile.inc

diff --git a/Makefile.inc b/Makefile.inc
index 19377c9e1c..d1d09ab271 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -85,6 +85,7 @@ subdirs-y += src/mainboard/$(MAINBOARDDIR)
 subdirs-y += payloads payloads/external
 
 subdirs-y += site-local
+subdirs-y += util/checklist
 
 #######################################################################
 # Add source classes and their build options
diff --git a/src/Kconfig b/src/Kconfig
index 6e6e9447ff..4eda5378f9 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1174,3 +1174,33 @@ config DEBUG_BOOT_STATE
 	help
 	  Control debugging of the boot state machine.  When selected displays
 	  the state boundaries in ramstage.
+
+config CREATE_BOARD_CHECKLIST
+	bool
+	default n
+	help
+	  When selected, creates a webpage showing the implementation status for
+	  the board.  Routines highlighted in green are complete, yellow are
+	  optional and red are required and must be implemented.  A table is
+	  produced for each stage of the boot process except the bootblock.  The
+	  red items may be used as an implementation checklist for the board.
+
+config MAKE_CHECKLIST_PUBLIC
+	bool
+	default n
+	help
+	  When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
+	  is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
+	  directory.
+
+config CHECKLIST_DATA_FILE_LOCATION
+	string
+	help
+	  Location of the <stage>_complete.dat and <stage>_optional.dat files
+	  that are consumed during checklist processing.  <stage>_complete.dat
+	  contains the symbols that are expected to be in the resulting image.
+	  <stage>_optional.dat is a subset of <stage>_complete.dat and contains
+	  a list of weak symbols which the resulting image may consume.  Other
+	  symbols contained only in <stage>_complete.dat will be flagged as
+	  required and not implemented if a weak implementation is found in the
+	  resulting image.
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 9b2c463878..86f6c7b99e 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -115,4 +115,8 @@ config VBT_FILE
 	depends on GOP_SUPPORT
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin"
 
+config CHECKLIST_DATA_FILE_LOCATION
+	string
+	default "src/vendorcode/intel/fsp/fsp1_1/checklist"
+
 endif #PLATFORM_USES_FSP1_1
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat
new file mode 100644
index 0000000000..8a4325f4e0
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat
@@ -0,0 +1,77 @@
+arch_segment_loaded
+backup_top_of_ram
+bootblock_mainboard_early_init
+bootblock_mainboard_init
+bootblock_soc_early_init
+bootblock_soc_init
+boot_device_init
+car_mainboard_post_console_init
+car_mainboard_pre_console_init
+car_soc_post_console_init
+car_soc_pre_console_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fill_power_state
+fw_cfg_acpi_tables
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+init_timer
+lb_board
+lb_framebuffer
+mainboard_add_dimm_info
+mainboard_check_ec_image
+mainboard_io_trap_handler
+mainboard_memory_init_params
+mainboard_post
+mainboard_romstage_entry
+mainboard_save_dimm_info
+mainboard_silicon_init_params
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+mainboard_suspend_resume
+map_oprom_vendev
+mirror_payload
+mrc_cache_get_current
+mrc_cache_stash_data
+northbridge_smi_handler
+nvm_mmio_to_flash_offset
+platform_prog_run
+platform_segment_loaded
+raminit
+ramstage_cache_invalid
+report_memory_config
+save_chromeos_gpios
+setup_stack_and_mtrrs
+smbios_mainboard_bios_version
+smbios_mainboard_manufacturer
+smbios_mainboard_product_name
+smbios_mainboard_serial_number
+smbios_mainboard_set_uuid
+smbios_mainboard_version
+smm_disable_busmaster
+soc_after_ram_init
+soc_after_silicon_init
+soc_display_memory_init_params
+soc_display_silicon_init_params
+soc_fill_acpi_wake
+soc_memory_init_params
+soc_pre_ram_init
+soc_silicon_init_params
+soc_skip_ucode_update
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+timestamp_tick_freq_mhz
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
+verstage_mainboard_init
+wifi_regulatory_domain
+write_smp_table
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat
new file mode 100644
index 0000000000..64f8584340
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat
@@ -0,0 +1,53 @@
+acpi_create_serialio_ssdt
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fw_cfg_acpi_tables
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+init_timer
+lb_board
+lb_framebuffer
+mainboard_add_dimm_info
+mainboard_io_trap_handler
+mainboard_post
+mainboard_silicon_init_params
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+mainboard_suspend_resume
+map_oprom_vendev
+mirror_payload
+northbridge_smi_handler
+nvm_mmio_to_flash_offset
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+smbios_mainboard_bios_version
+smbios_mainboard_manufacturer
+smbios_mainboard_product_name
+smbios_mainboard_serial_number
+smbios_mainboard_set_uuid
+smbios_mainboard_version
+smm_disable_busmaster
+soc_after_silicon_init
+soc_display_silicon_init_params
+soc_fill_acpi_wake
+soc_silicon_init_params
+soc_skip_ucode_update
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+timestamp_tick_freq_mhz
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+wifi_regulatory_domain
+write_smp_table
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat
new file mode 100644
index 0000000000..6608583b28
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat
@@ -0,0 +1,46 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fw_cfg_acpi_tables
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+lb_board
+lb_framebuffer
+mainboard_add_dimm_info
+mainboard_io_trap_handler
+mainboard_post
+mainboard_silicon_init_params
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+mainboard_suspend_resume
+map_oprom_vendev
+mirror_payload
+northbridge_smi_handler
+nvm_mmio_to_flash_offset
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+smbios_mainboard_bios_version
+smbios_mainboard_manufacturer
+smbios_mainboard_product_name
+smbios_mainboard_serial_number
+smbios_mainboard_set_uuid
+smbios_mainboard_version
+smm_disable_busmaster
+soc_after_silicon_init
+soc_display_silicon_init_params
+soc_silicon_init_params
+soc_skip_ucode_update
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+wifi_regulatory_domain
+write_smp_table
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
new file mode 100644
index 0000000000..e6bef6cf26
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
@@ -0,0 +1,54 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fill_power_state
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+init_timer
+mainboard_add_dimm_info
+mainboard_check_ec_image
+mainboard_fill_spd_data
+mainboard_io_trap_handler
+mainboard_memory_init_params
+mainboard_post
+mainboard_romstage_entry
+mainboard_save_dimm_info
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+map_oprom_vendev
+migrate_power_state
+mrc_cache_get_current_with_version
+mrc_cache_stash_data_with_version
+platform_prog_run
+platform_segment_loaded
+print_fsp_info
+raminit
+ramstage_cache_invalid
+report_memory_config
+romstage_common
+save_chromeos_gpios
+set_max_freq
+setup_stack_and_mtrrs
+smm_region
+smm_region_size
+soc_after_ram_init
+soc_display_memory_init_params
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+soc_memory_init_params
+soc_pre_ram_init
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
new file mode 100644
index 0000000000..2634566528
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
@@ -0,0 +1,34 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+mainboard_add_dimm_info
+mainboard_check_ec_image
+mainboard_io_trap_handler
+mainboard_post
+mainboard_romstage_entry
+mainboard_save_dimm_info
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+map_oprom_vendev
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+soc_after_ram_init
+soc_display_memory_init_params
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+soc_memory_init_params
+soc_pre_ram_init
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
new file mode 100644
index 0000000000..2124f0f2e5
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
@@ -0,0 +1,35 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+car_mainboard_post_console_init
+car_mainboard_pre_console_init
+car_soc_post_console_init
+car_soc_pre_console_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+get_sw_write_protect_state
+gpio_acpi_path
+init_timer
+mainboard_check_ec_image
+mainboard_io_trap_handler
+mainboard_post
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+map_oprom_vendev
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
+verstage_mainboard_init
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
new file mode 100644
index 0000000000..f589eaa919
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
@@ -0,0 +1,22 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+car_mainboard_post_console_init
+car_mainboard_pre_console_init
+car_soc_post_console_init
+car_soc_pre_console_init
+mainboard_check_ec_image
+mainboard_post
+platform_prog_run
+platform_segment_loaded
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
+verstage_mainboard_init
diff --git a/util/checklist/Makefile.inc b/util/checklist/Makefile.inc
new file mode 100644
index 0000000000..f8e5ebd5e6
--- /dev/null
+++ b/util/checklist/Makefile.inc
@@ -0,0 +1,260 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2016 Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+###########################################################################
+# Build the board implementation checklist
+###########################################################################
+
+# Only build the checklist for boards under development
+ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y)
+
+#
+# Extract the symbol table from the image
+#
+%.symbol_table: %.elf %.debug
+	$(NM_$(class)) $< > $@
+	$(NM_$(class)) $(*D)/$(*F).debug >> $@
+
+#
+# All symbols in the image
+#
+# 1. Remove the address and symbol type
+# 2. Sort the table into alphabetical order
+# 3. Remove any duplicates
+#
+%.symbols: %.symbol_table
+	sed 's/^...........//' $< > $@.tmp
+	sort $@.tmp > $@.tmp2
+	uniq $@.tmp2 > $@
+	rm $@.tmp $@.tmp2
+
+#
+# Weak symbols in the image
+#
+# 1. Find the weak symbols
+# 2. Remove the address and symbol type
+# 3. Sort the table into alphabetical order
+# 4. Remove any duplicates
+#
+%.weak: %.symbol_table
+	grep -F " W " $< | sed 's/^...........//' > $@.tmp
+	sort $@.tmp > $@.tmp2
+	uniq $@.tmp2 > $@
+	rm $@.tmp $@.tmp2
+
+#
+# Expected symbols in the image
+#
+# 1. Get the complete list of expected symbols in the image
+# 2. Sort the table into alphabetical order
+# 3. Remove any duplicates
+#
+%.expected: %.symbol_table
+	cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp
+	# If no separate verstage, combine verstage and romstage routines into a single list
+	if [ "$(*F)" = "romstage" ]; then \
+	  if [ ! -e $(*D)/verstage.elf ]; then \
+	    if [ ! -e $(*D)/postcar.elf ]; then \
+	      cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat >> $@.tmp; \
+	    fi; \
+	  fi; \
+	fi
+	sort $@.tmp > $@.tmp2
+	uniq $@.tmp2 > $@
+	rm $@.tmp $@.tmp2
+
+#
+# Optional symbols in the image
+#
+# 1. Get the list of optional symbols in the image
+# 2. Sort the table into alphabetical order
+# 3. Remove any duplicates
+#
+%.optional: %.symbol_table
+	cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $@.tmp
+	# If no separate verstage, combine verstage and romstage routines into a single list
+	if [ "$(*F)" = "romstage" ]; then \
+	  if [ ! -e $(*D)/verstage.elf ]; then \
+	    if [ ! -e $(*D)/postcar.elf ]; then \
+	      cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \
+	    fi; \
+	  fi; \
+	fi
+	sort $@.tmp > $@.tmp2
+	uniq $@.tmp2 > $@
+	rm $@.tmp $@.tmp2
+
+#
+#   Expected Symbols Optional	Weak	Done	Type
+#	no	yes	no	d/c	yes	Don't display
+#	yes	no	no	no	no	Required - not implemented
+#	yes	no	yes	no	no	Optional - not implemented
+#	yes	yes	yes	yes	no	Optional - not implemented
+#	yes	yes	no	no	yes	Required - implemented
+#	yes	yes	yes	no	yes	Required - implemented
+#
+# Implemented routines are in the symbol table and are not weak
+#
+# 1. Remove expected symbols which are not in the image (not implemented yet)
+# 2. Remove weak symbols from the list (not implemented yet)
+#
+%.done: %.symbols %.expected %.weak %.optional
+	comm -12 $(*D)/$(*F).expected $(*D)/$(*F).symbols | sed "s/^[ \t]*//" > $@.tmp
+	comm -23 $@.tmp $(*D)/$(*F).weak | sed "s/^[ \t]*//" > $@
+	rm $@.tmp
+
+#
+# Remove any routines that are implemented
+#
+%.optional2: %.optional %.done
+	comm -23 $^ | sed "s/^[ \t]*//" > $@
+
+#
+# Remove any implemented or optional routines
+#
+%.tbd: %.expected %.done %.optional2
+	comm -23 $(*D)/$(*F).expected $(*D)/$(*F).done | sed "s/^[ \t]*//" > $@.tmp
+	comm -23 $@.tmp $(*D)/$(*F).optional2 | sed "s/^[ \t]*//" > $@
+	rm $@.tmp
+
+#
+# Build the implementation table for each stage
+# 1. Color code the rows
+#    *  Done table rows are in green
+#    *  Optional table rows are in yellow
+#    *  TBD table rows are in red
+# 2. Add the row termination
+# 3. Sort the rows into alphabetical order
+#
+%.table_rows: %.optional2 %.done %.expected %.tbd
+	sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp
+	sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional2 >> $@.tmp
+	if [ -s $(*D)/$(basename $(*F)).tbd ]; then \
+	  sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).tbd >> $@.tmp; \
+	fi
+	sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp
+	sort -t ">" -k4 $@.tmp > $@
+	rm $@.tmp
+
+#
+# Count the lines in the done file
+#
+done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//')
+
+#
+# Count the lines in the optional file
+#
+optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional2 | sed 's/ .*//')
+
+#
+# Count the lines in the expected file
+#
+expected_lines = $$(wc -l $(*D)/$(basename $(*F)).expected | sed 's/ .*//')
+
+# Compute the percentage done by routine count
+percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lines))))
+
+#
+# Build the table
+# 1. Add the table header
+# 2. Add the table rows
+# 3. Add the table trailer
+#
+%.html: %.table_rows
+	echo "<table border=1>" > $@
+	echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@
+	echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@
+	cat $< >> $@
+	echo "</table>" >> $@
+
+#
+# Determine which HTML files to include into the webpage
+#
+ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
+html_table_files += $(objcbfs)/verstage.html
+endif
+ifeq ($(CONFIG_POSTCAR_STAGE),y)
+html_table_files += $(objcbfs)/postcar.html
+endif
+html_table_files += $(objcbfs)/romstage.html $(objcbfs)/ramstage.html
+
+#
+# Create a list with each file on a separate line
+#
+list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files})
+
+#
+# Get the date for the webpage
+#
+current_date_time = $$(date +"%Y/%m/%d %T %Z")
+
+#
+# Build the webpage from the implementation tables
+# 1. Add the header to the webpage
+# 2. Add the legend to the webpage
+# 3. Use a table to place stage tables side-by-side
+# 4. Add the stage tables to the webpage
+# 5. Separate the stage tables
+# 6. Terminate the outer table
+# 7. Add the trailer to the webpage
+#
+$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files)
+	echo "<html>" > $@
+	echo "<head>" >> $@
+	echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@
+	echo "</title>" >> $@
+	echo "<body>" >> $@
+	echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status<br>$(current_date_time)</h1>" >> $@
+	echo "<table>" >> $@
+	echo "  <tr><td colspan=2><b>Legend</b></td></tr>" >> $@
+	echo "  <tr><td bgcolor=\"#ffc0c0\">Red</td><td>Required - To-be-implemented</td></tr>" >> $@
+	echo "  <tr><td bgcolor=\"#ffffc0\">Yellow</td><td>Optional</td></tr>" >> $@
+	echo "  <tr><td bgcolor=\"#c0ffc0\">Green</td><td>Implemented</td></tr>" >> $@
+	echo "</table>" >> $@
+	echo "<table>" >> $@
+	echo "  <tr valign=\"top\">" >> $@
+	for table in $(list_of_html_files); do \
+	  echo "    <td>" >> $@; \
+	  cat $$table >> $@; \
+	  echo "    </td>" >> $@; \
+	  echo "    <td width=5>&nbsp;</td>" >> $@; \
+	done
+	echo "  </tr>" >> $@
+	echo "</table>" >> $@
+	echo "</body>" >> $@
+	echo "</html>" >> $@
+
+#
+# Copy the output file into the Documentation directory
+#
+Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
+	if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; then \
+	  mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \
+	fi
+	if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; then \
+	  mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \
+	fi
+	cp $< $@
+
+#
+# Determine where to place the output file
+#
+ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y)
+INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
+else
+INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
+endif
+
+endif
-- 
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