From fc1c1b572f3523950cdf5cbf0c2967365700cfc3 Mon Sep 17 00:00:00 2001 From: York Yang Date: Tue, 4 Nov 2014 17:04:37 -0700 Subject: intel/fsp_baytrail: add Gold3 FSP support Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION making platform more configurable via devicetree.cb Update the UPD_DATA_REGION structure and pass settings to FSP Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3 FSP changes UPD_DATA_REGION struct Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6 Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/7334 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_baytrail/chip.h | 104 +++++++++++++++++ src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 129 ++++++++++++++++++++- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 4 + src/vendorcode/intel/fsp/baytrail/include/fspvpd.h | 116 ++++++++++-------- 4 files changed, 303 insertions(+), 50 deletions(-) mode change 100644 => 100755 src/soc/intel/fsp_baytrail/chip.h mode change 100644 => 100755 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c mode change 100644 => 100755 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h mode change 100644 => 100755 src/vendorcode/intel/fsp/baytrail/include/fspvpd.h diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h old mode 100644 new mode 100755 index 12eba10e8b..65377a62c5 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -172,6 +173,109 @@ struct soc_intel_fsp_baytrail_config { #define LPE_ACPI_MODE_DISABLED 1 #define LPE_ACPI_MODE_ENABLED 2 + uint32_t SerialDebugPortAddress; + #define SerialDebugPortAddress_DEFAULT 0 + + uint8_t SerialDebugPortType; + #define SERIAL_DEBUG_PORT_DEFAULT 0 + #define SERIAL_DEBUG_PORT_TYPE_NONE 1 + #define SERIAL_DEBUG_PORT_TYPE_IO 2 + #define SERIAL_DEBUG_PORT_TYPE_MMIO 3 + + uint8_t PcdMrcDebugMsg; + #define MRC_DEBUG_MSG_DEFAULT 0 + #define MRC_DEBUG_MSG_DISABLE 1 + #define MRC_DEBUG_MSG_ENABLE 2 + + uint8_t PcdSccEnablePciMode; + #define SCC_PCI_MODE_DEFAULT 0 + #define SCC_PCI_MODE_DISABLE 1 + #define SCC_PCI_MODE_ENABLE 2 + + uint8_t IgdRenderStandby; + #define IGD_RENDER_STANDBY_DEFAULT 0 + #define IGD_RENDER_STANDBY_DISABLE 1 + #define IGD_RENDER_STANDBY_ENABLE 2 + + uint8_t TxeUmaEnable; + #define TXE_UMA_DEFAULT 0 + #define TXE_UMA_DISABLE 1 + #define TXE_UMA_ENABLE 2 + + /* Memory down data */ + uint8_t EnableMemoryDown; + #define MEMORY_DOWN_DEFAULT 0 + #define MEMORY_DOWN_DISABLE 1 + #define MEMORY_DOWN_ENABLE 2 + + uint8_t DRAMSpeed; + #define DRAM_SPEED_DEFAULT 0 + #define DRAM_SPEED_800MHZ 1 + #define DRAM_SPEED_1066MHZ 2 + #define DRAM_SPEED_1333MHZ 3 + #define DRAM_SPEED_1600MHZ 4 + + uint8_t DRAMType; + #define DRAM_TYPE_DEFAULT 0 + #define DRAM_TYPE_DDR3 1 + #define DRAM_TYPE_DDR3L 2 + + uint8_t DIMM0Enable; + #define DIMM0_ENABLE_DEFAULT 0 + #define DIMM0_DISABLE 1 + #define DIMM0_ENABLE 2 + + uint8_t DIMM1Enable; + #define DIMM1_ENABLE_DEFAULT 0 + #define DIMM1_DISABLE 1 + #define DIMM1_ENABLE 2 + + uint8_t DIMMDWidth; + #define DIMM_DWIDTH_DEFAULT 0 + #define DIMM_DWIDTH_X8 1 + #define DIMM_DWIDTH_X16 2 + #define DIMM_DWIDTH_X32 3 + + uint8_t DIMMDensity; + #define DIMM_DENSITY_DEFAULT 0 + #define DIMM_DENSITY_1G_BIT 1 + #define DIMM_DENSITY_2G_BIT 2 + #define DIMM_DENSITY_4G_BIT 3 + #define DIMM_DENSITY_8G_BIT 4 + + uint8_t DIMMBusWidth; + #define DIMM_BUS_WIDTH_DEFAULT 0 + #define DIMM_BUS_WIDTH_8BIT 1 + #define DIMM_BUS_WIDTH_16BIT 2 + #define DIMM_BUS_WIDTH_32BIT 3 + #define DIMM_BUS_WIDTH_64BIT 4 + + uint8_t DIMMSides; + #define DIMM_SIDES_DEFAULT 0 + #define DIMM_SIDES_1RANK 1 + #define DIMM_SIDES_2RANK 2 + + uint8_t DIMMtCL; + #define DIMM_TCL_DEFAULT 0 + + uint8_t DIMMtRPtRCD; + #define DIMM_TRP_TRCD_DEFAULT 0 + + uint8_t DIMMtWR; + #define DIMM_TWR_DEFAULT 0 + + uint8_t DIMMtWTR; + #define DIMM_TWTR_DEFAULT 0 + + uint8_t DIMMtRRD; + #define DIMM_TRRD_DEFAULT 0 + + uint8_t DIMMtRTP; + #define DIMM_TRTP_DEFAULT 0 + + uint8_t DIMMtFAW; + #define DIMM_TFAW_DEFAULT 0 + /* ***** ACPI configuration ***** */ /* Options for these are in src/arch/x86/include/arch/acpi.h */ uint8_t fadt_pm_profile; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c old mode 100644 new mode 100755 index 2a41e612a3..45b4154492 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -69,7 +70,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t; * * @param UpdData Pointer to the UPD Data structure */ -static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) +static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { ROMSTAGE_CONST struct device *dev; ROMSTAGE_CONST config_t *config; @@ -146,7 +147,15 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) switch (dev->path.pci.devfn) { case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ - UpdData->ISPEnable = dev->enabled; + if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { + UpdData->ISPEnable = dev->enabled; + } else { + /* Gold2 and earlier FSP: ISPEnable is the filed */ + /* next to PcdGttSize in UPD_DATA_REGION struct */ + *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; + printk (BIOS_DEBUG, + "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); + } printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n", UpdData->PcdEnableSdio?"Enabled":"Disabled"); break; @@ -303,6 +312,120 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n", UpdData->PcdEnableXhci?"Enabled":"Disabled"); + if (config->SerialDebugPortAddress != SerialDebugPortAddress_DEFAULT) { + UpdData->SerialDebugPortAddress = config->SerialDebugPortAddress; + } + if (config->SerialDebugPortType != SERIAL_DEBUG_PORT_DEFAULT) { + UpdData->SerialDebugPortType + = config->SerialDebugPortType - SERIAL_DEBUG_PORT_TYPE_NONE; + } + if (config->PcdMrcDebugMsg != MRC_DEBUG_MSG_DEFAULT) { + UpdData->PcdMrcDebugMsg + = config->PcdMrcDebugMsg - MRC_DEBUG_MSG_DISABLE; + printk (BIOS_DEBUG, "MRC Debug Message:\t%s\n", + (UpdData->PcdMrcDebugMsg) ? "Enabled" : "Disabled"); + } + if (config->PcdSccEnablePciMode != SCC_PCI_MODE_DEFAULT) { + UpdData->PcdSccEnablePciMode + = config->PcdSccEnablePciMode - SCC_PCI_MODE_DISABLE; + } + if (config->IgdRenderStandby != IGD_RENDER_STANDBY_DEFAULT) { + UpdData->IgdRenderStandby + = config->IgdRenderStandby - IGD_RENDER_STANDBY_DISABLE; + printk (BIOS_DEBUG, "IGD Render Standby:\t%s\n", + (UpdData->IgdRenderStandby) ? "Enabled" : "Disabled"); + } + if (config->TxeUmaEnable != TXE_UMA_DEFAULT) { + UpdData->TxeUmaEnable = config->TxeUmaEnable - TXE_UMA_DISABLE; + } + + /* set memory down parameters */ + if (config->EnableMemoryDown != MEMORY_DOWN_DEFAULT) { + UpdData->PcdMemoryParameters.EnableMemoryDown + = config->EnableMemoryDown - MEMORY_DOWN_DISABLE; + + if (config->DRAMSpeed != DRAM_SPEED_DEFAULT) { + UpdData->PcdMemoryParameters.DRAMSpeed + = config->DRAMSpeed - DRAM_SPEED_800MHZ; + } + if (config->DRAMType != DRAM_TYPE_DEFAULT) { + UpdData->PcdMemoryParameters.DRAMType + = config->DRAMType - DRAM_TYPE_DDR3; + } + if (config->DIMM0Enable != DIMM0_ENABLE_DEFAULT) { + UpdData->PcdMemoryParameters.DIMM0Enable + = config->DIMM0Enable - DIMM0_DISABLE; + } + if (config->DIMM1Enable != DIMM1_ENABLE_DEFAULT) { + UpdData->PcdMemoryParameters.DIMM1Enable + = config->DIMM1Enable - DIMM1_DISABLE; + } + if (config->DIMMDWidth != DIMM_DWIDTH_DEFAULT) { + UpdData->PcdMemoryParameters.DIMMDWidth + = config->DIMMDWidth - DIMM_DWIDTH_X8; + } + if (config->DIMMDensity != DIMM_DENSITY_DEFAULT) { + UpdData->PcdMemoryParameters.DIMMDensity + = config->DIMMDensity - DIMM_DENSITY_1G_BIT; + } + if (config->DIMMBusWidth != DIMM_BUS_WIDTH_DEFAULT) { + UpdData->PcdMemoryParameters.DIMMBusWidth + = config->DIMMBusWidth - DIMM_BUS_WIDTH_8BIT; + } + if (config->DIMMSides != DIMM_SIDES_DEFAULT) { + UpdData->PcdMemoryParameters.DIMMSides + = config->DIMMSides - DIMM_SIDES_1RANK; + } + if (config->DIMMtCL != DIMM_TCL_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtCL = config->DIMMtCL; + if (config->DIMMtRPtRCD != DIMM_TRP_TRCD_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtRPtRCD = config->DIMMtRPtRCD; + if (config->DIMMtWR != DIMM_TWR_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtWR = config->DIMMtWR; + if (config->DIMMtWTR != DIMM_TWTR_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtWTR = config->DIMMtWTR; + if (config->DIMMtRRD != DIMM_TRRD_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtRRD = config->DIMMtRRD; + if (config->DIMMtRTP != DIMM_TRTP_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtRTP = config->DIMMtRTP; + if (config->DIMMtFAW != DIMM_TFAW_DEFAULT) + UpdData->PcdMemoryParameters.DIMMtFAW = config->DIMMtFAW; + + printk (BIOS_DEBUG, + "Memory Down Data Existed : %s\n"\ + "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ + "- Type (0: DDR3, 1: DDR3L) : %d\n"\ + "- DIMM0 : %s\n"\ + "- DIMM1 : %s\n"\ + "- Width : x%d\n"\ + "- Density : %dGbit\n" + "- BudWidth : %dbit\n"\ + "- Rank # : %d\n"\ + "- tCL : %02X\n"\ + "- tRPtRCD : %02X\n"\ + "- tWR : %02X\n"\ + "- tWTR : %02X\n"\ + "- tRRD : %02X\n"\ + "- tRTP : %02X\n"\ + "- tFAW : %02X\n" + , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" + , UpdData->PcdMemoryParameters.DRAMSpeed + , UpdData->PcdMemoryParameters.DRAMType + , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" + , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" + , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) + , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) + , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) + , (UpdData->PcdMemoryParameters.DIMMSides) + 1 + , UpdData->PcdMemoryParameters.DIMMtCL + , UpdData->PcdMemoryParameters.DIMMtRPtRCD + , UpdData->PcdMemoryParameters.DIMMtWR + , UpdData->PcdMemoryParameters.DIMMtWTR + , UpdData->PcdMemoryParameters.DIMMtRRD + , UpdData->PcdMemoryParameters.DIMMtRTP + , UpdData->PcdMemoryParameters.DIMMtFAW + ); + } } /* Set up the Baytrail specific structures for the call into the FSP */ @@ -318,7 +441,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); + ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h old mode 100644 new mode 100755 index 1b603986ea..6df14845d8 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -46,4 +47,7 @@ #define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ #define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ +/* Revision of the FSP binary */ +#define FSP_GOLD3_REV_ID 0x00000303 + #endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h old mode 100644 new mode 100755 index 1b820a8eec..b001cdb28c --- a/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -28,56 +28,78 @@ are permitted provided that the following conditions are met: **/ -/** - -This file is auto-generated, please DO NOT modify. +#ifndef __FSPVPD_H__ +#define __FSPVPD_H__ -**/ +#pragma pack(1) -#ifndef __VPDHEADER_H__ -#define __VPDHEADER_H__ +typedef struct { + UINT8 EnableMemoryDown; + UINT8 DRAMSpeed; /* DRAM Speed */ + UINT8 DRAMType; /* DRAM Type */ + UINT8 DIMM0Enable; /* DIMM 0 Enable */ + UINT8 DIMM1Enable; /* DIMM 1 Enable */ + UINT8 DIMMDWidth; /* DRAM device data width */ + UINT8 DIMMDensity; /* DRAM device data density */ + UINT8 DIMMBusWidth; /* DIMM Bus Width */ + UINT8 DIMMSides; /* Ranks Per DIMM */ + UINT8 DIMMtCL; /* tCL */ + UINT8 DIMMtRPtRCD; /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ + UINT8 DIMMtWR; /* tWR in DRAM clk */ + UINT8 DIMMtWTR; /* tWTR in DRAM clk */ + UINT8 DIMMtRRD; /* tRRD in DRAM clk */ + UINT8 DIMMtRTP; /* tRTP in DRAM clk */ + UINT8 DIMMtFAW; /* tFAW in DRAM clk */ +} MEMORY_DOWN_DATA; -#pragma pack(1) typedef struct _UPD_DATA_REGION { - UINT64 Signature; /* Offset 0x0000 */ - UINT32 RESERVED1; /* Offset 0x0008 */ - UINT8 Padding0[20]; /* Offset 0x000C */ - UINT16 PcdMrcInitTsegSize; /* Offset 0x0014 */ - UINT16 PcdMrcInitMmioSize; /* Offset 0x0016 */ - UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0018 */ - UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0019 */ - UINT8 PcdeMMCBootMode; /* Offset 0x001B */ - UINT8 PcdEnableSdio; /* Offset 0x001C */ - UINT8 PcdEnableSdcard; /* Offset 0x001D */ - UINT8 PcdEnableHsuart0; /* Offset 0x001E */ - UINT8 PcdEnableHsuart1; /* Offset 0x001F */ - UINT8 PcdEnableSpi; /* Offset 0x0020 */ - UINT8 PcdEnableLan; /* Offset 0x0021 */ - UINT8 PcdEnableSata; /* Offset 0x0023 */ - UINT8 PcdSataMode; /* Offset 0x002E */ - UINT8 PcdEnableAzalia; /* Offset 0x002F */ - UINT32 AzaliaConfigPtr; /* Offset 0x0030 */ - UINT8 PcdEnableXhci; /* Offset 0x0034 */ - UINT8 PcdEnableLpe; /* Offset 0x0029 */ - UINT8 PcdLpssSioEnablePciMode; /* Offset 0x002A */ - UINT8 PcdEnableDma0; /* Offset 0x002B */ - UINT8 PcdEnableDma1; /* Offset 0x002C */ - UINT8 PcdEnableI2C0; /* Offset 0x002D */ - UINT8 PcdEnableI2C1; /* Offset 0x002E */ - UINT8 PcdEnableI2C2; /* Offset 0x002F */ - UINT8 PcdEnableI2C3; /* Offset 0x0030 */ - UINT8 PcdEnableI2C4; /* Offset 0x0031 */ - UINT8 PcdEnableI2C5; /* Offset 0x0032 */ - UINT8 PcdEnableI2C6; /* Offset 0x0033 */ - UINT8 PcdEnablePwm0; /* Offset 0x0034 */ - UINT8 PcdEnablePwm1; /* Offset 0x0035 */ - UINT8 PcdEnableHsi; /* Offset 0x0036 */ - UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */ - UINT8 PcdApertureSize; /* Offset 0x0044 */ - UINT8 PcdGttSize; /* Offset 0x0045 */ - UINT8 ISPEnable; /* Offset 0x0046 */ - UINT16 PcdRegionTerminator; /* Offset 0x0047 */ + UINT64 Signature; /* Offset 0x0000 */ + UINT32 RESERVED1; /* Offset 0x0008 */ + UINT8 Padding0[20]; /* Offset 0x000C */ + UINT16 PcdMrcInitTsegSize; /* Offset 0x0020 */ + UINT16 PcdMrcInitMmioSize; /* Offset 0x0022 */ + UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0024 */ + UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0025 */ + UINT8 PcdeMMCBootMode; /* Offset 0x0026 */ + UINT8 PcdEnableSdio; /* Offset 0x0027 */ + UINT8 PcdEnableSdcard; /* Offset 0x0028 */ + UINT8 PcdEnableHsuart0; /* Offset 0x0029 */ + UINT8 PcdEnableHsuart1; /* Offset 0x002A */ + UINT8 PcdEnableSpi; /* Offset 0x002B */ + UINT8 PcdEnableLan; /* Offset 0x002C */ + UINT8 PcdEnableSata; /* Offset 0x002D */ + UINT8 PcdSataMode; /* Offset 0x002E */ + UINT8 PcdEnableAzalia; /* Offset 0x002F */ + UINT32 AzaliaConfigPtr; /* Offset 0x0030 */ + UINT8 PcdEnableXhci; /* Offset 0x0034 */ + UINT8 PcdEnableLpe; /* Offset 0x0035 */ + UINT8 PcdLpssSioEnablePciMode; /* Offset 0x0036 */ + UINT8 PcdEnableDma0; /* Offset 0x0037 */ + UINT8 PcdEnableDma1; /* Offset 0x0038 */ + UINT8 PcdEnableI2C0; /* Offset 0x0039 */ + UINT8 PcdEnableI2C1; /* Offset 0x003A */ + UINT8 PcdEnableI2C2; /* Offset 0x003B */ + UINT8 PcdEnableI2C3; /* Offset 0x003C */ + UINT8 PcdEnableI2C4; /* Offset 0x003D */ + UINT8 PcdEnableI2C5; /* Offset 0x003E */ + UINT8 PcdEnableI2C6; /* Offset 0x003F */ + UINT8 PcdEnablePwm0; /* Offset 0x0040 */ + UINT8 PcdEnablePwm1; /* Offset 0x0041 */ + UINT8 PcdEnableHsi; /* Offset 0x0042 */ + UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */ + UINT8 PcdApertureSize; /* Offset 0x0044 */ + UINT8 PcdGttSize; /* Offset 0x0045 */ + UINT32 SerialDebugPortAddress; /* Offset 0x0046 */ + UINT8 SerialDebugPortType; /* Offset 0x004A */ + UINT8 PcdMrcDebugMsg; /* Offset 0x004B */ + UINT8 ISPEnable; /* Offset 0x004C */ + UINT8 PcdSccEnablePciMode; /* Offset 0x004D */ + UINT8 IgdRenderStandby; /* Offset 0x004E */ + UINT8 TxeUmaEnable; /* Offset 0x004F */ + UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */ + MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ + UINT16 PcdRegionTerminator; /* Offset 0x0100 */ } UPD_DATA_REGION; @@ -86,7 +108,7 @@ typedef struct _VPD_DATA_REGION { UINT32 PcdImageRevision; /* Offset 0x0008 */ UINT32 PcdUpdRegionOffset; /* Offset 0x000C */ UINT8 Padding0[16]; /* Offset 0x0010 */ - UINT32 RESERVED1; /* Offset 0x0020 */ + UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */ UINT8 PcdPlatformType; /* Offset 0x0024 */ UINT8 PcdEnableSecureBoot; /* Offset 0x0025 */ UINT8 PcdMemoryParameters[16]; /* Offset 0x0026 */ -- cgit v1.2.3