From fad9536edf408718ddbc65c664652b6c01267568 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 30 Aug 2019 10:41:25 +0300 Subject: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They don't benefit from having low-memory set as writeback-cacheable. This also fixes regression from CB:34893 that caused some random hangs with more recent intel SoCs in ramstage. BUG=b:140250314 Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Arthur Heymans --- src/arch/x86/postcar_loader.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 6a7d389ea3..61a9d52cd8 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -125,9 +125,6 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf) if (pcf->skip_common_mtrr) return; - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } -- cgit v1.2.3