From fa2df758f226f5b06537c6e6f8e27072b94644c5 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 27 Aug 2003 14:33:13 +0000 Subject: support for new mobos and fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/device/pci_ids.h | 2 + src/mainboard/tyan/s2880/Config.lb | 27 ++-- src/mainboard/tyan/s2880/auto.c | 10 +- src/mainboard/tyan/s2880/chip.h | 1 + src/mainboard/tyan/s2880/mainboard.c | 144 ++++++++++--------- src/mainboard/tyan/s2882/Config.lb | 175 ++++++++++++++++++++++++ src/mainboard/tyan/s2882/VERSION | 1 + src/mainboard/tyan/s2882/auto.c | 211 ++++++++++++++++++++++++++++ src/mainboard/tyan/s2882/chip.h | 6 + src/mainboard/tyan/s2882/cmos.layout | 74 ++++++++++ src/mainboard/tyan/s2882/failover.c | 46 +++++++ src/mainboard/tyan/s2882/irq_tables.c | 39 ++++++ src/mainboard/tyan/s2882/mainboard.c | 174 +++++++++++++++++++++++ src/mainboard/tyan/s2882/mptable.c | 140 +++++++++++++++++++ src/mainboard/tyan/s2885/Config.lb | 178 ++++++++++++++++++++++++ src/mainboard/tyan/s2885/VERSION | 1 + src/mainboard/tyan/s2885/auto.c | 213 +++++++++++++++++++++++++++++ src/mainboard/tyan/s2885/chip.h | 6 + src/mainboard/tyan/s2885/cmos.layout | 74 ++++++++++ src/mainboard/tyan/s2885/failover.c | 46 +++++++ src/mainboard/tyan/s2885/irq_tables.c | 35 +++++ src/mainboard/tyan/s2885/mainboard.c | 174 +++++++++++++++++++++++ src/mainboard/tyan/s2885/mptable.c | 146 ++++++++++++++++++++ src/mainboard/tyan/s2885/ti_firewire.c | 44 ++++++ src/southbridge/amd/amd8151/Config.lb | 1 + src/southbridge/amd/amd8151/amd8151_agp3.c | 75 ++++++++++ targets/tyan/s2880/Config.lb | 131 ++++++++++++++---- 27 files changed, 2067 insertions(+), 107 deletions(-) create mode 100644 src/mainboard/tyan/s2882/Config.lb create mode 100644 src/mainboard/tyan/s2882/VERSION create mode 100644 src/mainboard/tyan/s2882/auto.c create mode 100644 src/mainboard/tyan/s2882/chip.h create mode 100644 src/mainboard/tyan/s2882/cmos.layout create mode 100644 src/mainboard/tyan/s2882/failover.c create mode 100644 src/mainboard/tyan/s2882/irq_tables.c create mode 100644 src/mainboard/tyan/s2882/mainboard.c create mode 100644 src/mainboard/tyan/s2882/mptable.c create mode 100644 src/mainboard/tyan/s2885/Config.lb create mode 100644 src/mainboard/tyan/s2885/VERSION create mode 100644 src/mainboard/tyan/s2885/auto.c create mode 100644 src/mainboard/tyan/s2885/chip.h create mode 100644 src/mainboard/tyan/s2885/cmos.layout create mode 100644 src/mainboard/tyan/s2885/failover.c create mode 100644 src/mainboard/tyan/s2885/irq_tables.c create mode 100644 src/mainboard/tyan/s2885/mainboard.c create mode 100644 src/mainboard/tyan/s2885/mptable.c create mode 100644 src/mainboard/tyan/s2885/ti_firewire.c create mode 100644 src/southbridge/amd/amd8151/Config.lb create mode 100644 src/southbridge/amd/amd8151/amd8151_agp3.c diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 947bc6f6e4..23fc13c58f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -637,6 +637,7 @@ #define PCI_DEVICE_ID_PROMISE_20276 0x5275 #define PCI_DEVICE_ID_PROMISE_20277 0x7275 #define PCI_DEVICE_ID_PROMISE_5300 0x5300 +#define PCI_DEVICE_ID_PROMISE_20378 0x3373 #define PCI_VENDOR_ID_N9 0x105d #define PCI_DEVICE_ID_N9_I128 0x2309 @@ -1833,6 +1834,7 @@ #define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 #define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 #define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf +#define PCI_DEVICE_ID_ADAPTEC2_7902 0x8012 #define PCI_VENDOR_ID_ATRONICS 0x907f #define PCI_DEVICE_ID_ATRONICS_2015 0x2015 diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 3367cd552a..865a07d122 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -17,12 +17,15 @@ uses ARCH ### ##object mainboard.o config chip.h -register "fixup_scsi" = "1" +register "fixup_scsi" = "1" +register "fixup_vga" = "1" + driver mainboard.o driver lsi_scsi.o -driver adaptec_scsi.o -driver intel_nic.o +#driver adaptec_scsi.o +driver promise_sata.o +#driver intel_nic.o object static_devices.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end @@ -45,7 +48,7 @@ if USE_FALLBACK_IMAGE mainboardinit cpu/i386/reset16.inc ldscript /cpu/i386/reset16.lds else - print "NO FALLBACK USED!" +# print "NO FALLBACK USED!" end if USE_NORMAL_IMAGE @@ -152,9 +155,9 @@ mainboardinit cpu/k8/disable_mmx_sse.inc ### northbridge amd/amdk8 end -southbridge amd/amd8111 +southbridge amd/amd8111 "amd8111" end -southbridge amd/amd8131 +southbridge amd/amd8131 "amd8131" end #mainboardinit archi386/smp/secondary.inc #superio NSC/pc87360 @@ -163,7 +166,11 @@ end #end dir /pc80 ##dir /src/superio/winbond/w83627hf -cpu p5 end -cpu p6 end -cpu k7 end -cpu k8 end +dir /bioscall +dir /cpu/k8 +cpu k8 "cpu0" + register "up" = "{.chip = &amd8131, .ht_width=8, .ht_speed=200}" +end + +cpu k8 "cpu1" +end diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c index 5dd6c673a0..5386b10d97 100644 --- a/src/mainboard/tyan/s2880/auto.c +++ b/src/mainboard/tyan/s2880/auto.c @@ -14,21 +14,21 @@ #include "lib/delay.c" #include "cpu/p6/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -//#include "debug.c" +#include "debug.c" static void memreset_setup(void) { /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); +// outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); +// outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); } static void memreset(int controllers, const struct mem_controller *ctrl) { udelay(800); /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); +// outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } @@ -179,7 +179,7 @@ static void main(void) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 +#if 1 dump_pci_devices(); #endif #if 0 diff --git a/src/mainboard/tyan/s2880/chip.h b/src/mainboard/tyan/s2880/chip.h index b867070275..d2b1b820d9 100644 --- a/src/mainboard/tyan/s2880/chip.h +++ b/src/mainboard/tyan/s2880/chip.h @@ -2,4 +2,5 @@ extern struct chip_control mainboard_tyan_s2880_control; struct mainboard_tyan_s2880_config { int fixup_scsi; + int fixup_vga; }; diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c index 446dd32bd4..8efc0a5d1b 100644 --- a/src/mainboard/tyan/s2880/mainboard.c +++ b/src/mainboard/tyan/s2880/mainboard.c @@ -11,7 +11,7 @@ unsigned long initial_apicid[MAX_CPUS] = { 0,1 }; -/* +#if 0 static void fixup_lsi_53c1030(struct device *pdev) { // uint8_t byte; @@ -35,9 +35,10 @@ static void fixup_lsi_53c1030(struct device *pdev) // lsi_scsi_init(pdev); } -*/ +#endif //extern static void lsi_scsi_init(struct device *dev); -/*static void print_pci_regs(struct device *dev) +#if 1 +static void print_pci_regs(struct device *dev) { uint8_t byte; int i; @@ -45,72 +46,67 @@ static void fixup_lsi_53c1030(struct device *pdev) for(i=0;i<256;i++) { byte = pci_read_config8(dev, i); - if((i%16)==0) printk_info("\n %02x:",i); - printk_debug(" %02x ",byte); + if((i%16)==0) printk_info("\n%02x:",i); + printk_debug(" %02x",byte); } - printk_debug("\r\n"); + printk_debug("\n"); // pci_write_config8(dev, 0x4, byte); } -*/ -static void onboard_scsi_fixup(void) +#endif +#if 0 +static void print_mem(void) { -// struct device *dev; - -/* // Set the scsi device id's - printk_debug("%2d:%2d:%2d\n",0,1,0); - dev = dev_find_slot(0, PCI_DEVFN(0x1, 0)); - if (dev) { - print_pci_regs(dev); - } - // Set the scsi device id's - printk_debug("%2d:%2d:%2d\n",0,2,0); - dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); - if (dev) { - print_pci_regs(dev); - } + int i; + int low_1MB = 0; + for(i=low_1MB;ifixup_scsi) onboard_scsi_fixup(); +// if (conf->fixup_vga) +// vga_fixup(); printk_debug("mainboard fixup pass %d done\r\n", pass); break; diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb new file mode 100644 index 0000000000..987012976c --- /dev/null +++ b/src/mainboard/tyan/s2882/Config.lb @@ -0,0 +1,175 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses USE_NORMAL_IMAGE +uses AMD8111_DEV +uses MAINBOARD +uses ARCH +# +# +### +### Set all of the defaults for an x86 architecture +### +# +# +### +### Build the objects we have code for in this directory. +### +##object mainboard.o +config chip.h +register "fixup_scsi" = "1" +register "fixup_vga" = "1" + + +driver mainboard.o +driver adaptec_scsi.o +#driver si_sata.o +#driver intel_nic.o +object static_devices.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +# +arch i386 end +#cpu k8 end +# +### +### Build our 16 bit and 32 bit linuxBIOS entry code +### +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript /cpu/i386/entry16.lds +ldscript /cpu/i386/entry32.lds +# +### +### Build our reset vector (This is where linuxBIOS is entered) +### +if USE_FALLBACK_IMAGE + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds +else +# print "NO FALLBACK USED!" +end + +if USE_NORMAL_IMAGE + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds +end +# +#### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc +# +### +### Include an id string (For safe flashing) +### +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +# +#### +#### This is the early phase of linuxBIOS startup +#### Things are delicate and we test to see if we should +#### failover to another image. +#### +#option MAX_REBOOT_CNT=2 +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +end +# +### +### Setup our mtrrs +### +mainboardinit cpu/k8/earlymtrr.inc +### +### Only the bootstrap cpu makes it here. +### Failover if we need to +### +# +if USE_FALLBACK_IMAGE + mainboardinit ./failover.inc +# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc +end + +# +# +### +### Setup the serial port +### +#mainboardinit superiowinbond/w83627hf/setup_serial.inc +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc +# +#### +#### O.k. We aren't just an intermediary anymore! +#### +# +### +### When debugging disable the watchdog timer +### +##option MAXIMUM_CONSOLE_LOGLEVEL=7 +#default MAXIMUM_CONSOLE_LOGLEVEL=7 +#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) +#if DISABLE_WATCHDOG +# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc +#end +# +#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end +# +### +### Romcc output +### +#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" +#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" +#mainboardinit .failover.inc + +makerule ./failover.E + depends "$(MAINBOARD)/failover.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" +end + +makerule ./failover.inc + depends "./romcc ./failover.E" + action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" +end +makerule ./auto.inc + depends "./romcc ./auto.E" + action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" +# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" +end +mainboardinit cpu/k8/enable_mmx_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/k8/disable_mmx_sse.inc +# +### +### Setup RAM +### +#mainboardinit ram/ramtest.inc +#mainboardinit southbridge/amd/amd8111/smbus.inc +#mainboardinit sdram/generic_dump_spd.inc +# +### +### Include the secondary Configuration files +### +northbridge amd/amdk8 +end +southbridge amd/amd8111 "amd8111" +end +southbridge amd/amd8131 "amd8131" +end +#mainboardinit archi386/smp/secondary.inc +#superio NSC/pc87360 +# register "com1" = "{1}" +# register "lpt" = "{1}" +#end +dir /pc80 +##dir /src/superio/winbond/w83627hf +dir /bioscall +dir /cpu/k8 +cpu k8 "cpu0" + register "up" = "{.chip = &amd8131, .ht_width=8, .ht_speed=200}" +end + +cpu k8 "cpu1" +end diff --git a/src/mainboard/tyan/s2882/VERSION b/src/mainboard/tyan/s2882/VERSION new file mode 100644 index 0000000000..cd5ac039d6 --- /dev/null +++ b/src/mainboard/tyan/s2882/VERSION @@ -0,0 +1 @@ +2.0 diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c new file mode 100644 index 0000000000..5386b10d97 --- /dev/null +++ b/src/mainboard/tyan/s2882/auto.c @@ -0,0 +1,211 @@ +#define ASSEMBLY 1 +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/k8/apic_timer.c" +#include "lib/delay.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "debug.c" + +static void memreset_setup(void) +{ + /* Set the memreset low */ +// outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ +// outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + udelay(800); + /* Set memreset_high */ +// outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); +} + +static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) +{ + /* Routing Table Node i + * + * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c + * i: 0, 1, 2, 3, 4, 5, 6, 7 + * + * [ 0: 3] Request Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + * [11: 8] Response Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + * [19:16] Broadcast route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + */ + + uint32_t ret=0x00010101; /* default row entry */ + + static const unsigned int rows_2p[2][2] = { + { 0x00050101, 0x00010404 }, + { 0x00010404, 0x00050101 } + }; + + if(maxnodes>2) { + print_debug("this mainboard is only designed for 2 cpus\r\n"); + maxnodes=2; + } + + + if (!(node>=maxnodes || row>=maxnodes)) { + ret=rows_2p[node][row]; + } + + return ret; +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/cpu_ldtstop.c" +#include "southbridge/amd/amd8111/amd8111_ldtstop.c" + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + +static void enable_lapic(void) +{ + msr_t msr; + msr = rdmsr(0x1b); + msr.hi &= 0xffffff00; + msr.lo &= 0x000007ff; + msr.lo |= APIC_DEFAULT_BASE | (1 << 11); + wrmsr(0x1b, msr); +} + +static void stop_this_cpu(void) +{ + unsigned apicid; + apicid = apic_read(APIC_ID) >> 24; + + /* Send an APIC INIT to myself */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); + + /* Deassert the APIC INIT */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); + + /* If I haven't halted spin forever */ + for(;;) { + hlt(); + } +} +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) +static void main(void) +{ + /* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ + static const struct mem_controller cpu[] = { +#if FIRST_CPU + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + }, +#endif +#if SECOND_CPU + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + }, +#endif + }; + if (cpu_init_detected()) { + asm("jmp __cpu_reset"); + } + enable_lapic(); + init_timer(); + if (!boot_cpu() ) { + notify_bsp_ap_is_stopped(); + stop_this_cpu(); + } + uart_init(); + console_init(); + setup_default_resource_map(); + setup_coherent_ht_domain(); + enumerate_ht_chain(0); + distinguish_cpu_resets(0); + +#if 0 + print_pci_devices(); +#endif + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + +#if 1 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 1)); +#endif + + /* Check all of memory */ +#if 0 + msr_t msr; + msr = rdmsr(TOP_MEM2); + print_debug("TOP_MEM2: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); +#endif +/* +#if 0 + ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#else +#if TOTAL_CPUS < 2 + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x01000000); +#else + // Check 16MB of memory @ 2GB + ram_check(0x80000000, 0x81000000); +#endif +#endif +*/ +} diff --git a/src/mainboard/tyan/s2882/chip.h b/src/mainboard/tyan/s2882/chip.h new file mode 100644 index 0000000000..a23805d043 --- /dev/null +++ b/src/mainboard/tyan/s2882/chip.h @@ -0,0 +1,6 @@ +extern struct chip_control mainboard_tyan_s2882_control; + +struct mainboard_tyan_s2882_config { + int fixup_scsi; + int fixup_vga; +}; diff --git a/src/mainboard/tyan/s2882/cmos.layout b/src/mainboard/tyan/s2882/cmos.layout new file mode 100644 index 0000000000..5ba4c032c1 --- /dev/null +++ b/src/mainboard/tyan/s2882/cmos.layout @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + diff --git a/src/mainboard/tyan/s2882/failover.c b/src/mainboard/tyan/s2882/failover.c new file mode 100644 index 0000000000..8b8bcb8b12 --- /dev/null +++ b/src/mainboard/tyan/s2882/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include +#include +#include +#include +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" +#if 0 +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#endif +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +static void main(void) +{ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ +#if 0 + uart_init(); + console_init(); +#endif + enumerate_ht_chain(0); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a cpu reset? */ + if (cpu_init_detected()) { + if (last_boot_normal()) { + asm("jmp __normal_image"); + } else { + asm("jmp __cpu_reset"); + } + } + /* Is this a secondary cpu? */ + else if (!boot_cpu() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + asm("jmp __normal_image"); + } +} diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c new file mode 100644 index 0000000000..09fccaf1ee --- /dev/null +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -0,0 +1,39 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*15, /* there can be total 15 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x3b, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x8d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, + {0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, + {0x3,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, + {0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, + {0x1,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, + {0x1,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, + {0x3,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, + {0x3,0x28, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x3,0x40, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x1,0x30, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0}, + {0x2,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0}, + {0x1,0x28, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x1,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + } +}; diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c new file mode 100644 index 0000000000..0862c87ac0 --- /dev/null +++ b/src/mainboard/tyan/s2882/mainboard.c @@ -0,0 +1,174 @@ +#include +#include +#include +#include +#include +#include +#include "chip.h" +//#include +//#include "lsi_scsi.c" +unsigned long initial_apicid[MAX_CPUS] = +{ + 0,1 +}; +#if 0 +static void fixup_lsi_53c1030(struct device *pdev) +{ +// uint8_t byte; + uint16_t word; + + byte = 1; + pci_write_config8(pdev, 0xff, byte); + // Set the device id +// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030); + // Set the subsytem vendor id +// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN); + word = 0x10f1; + pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word); + // Set the subsytem id + word = 0x2880; + pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word); + // Disable writes to the device id + byte = 0; + pci_write_config8(pdev, 0xff, byte); + +// lsi_scsi_init(pdev); + +} +#endif +//extern static void lsi_scsi_init(struct device *dev); +#if 1 +static void print_pci_regs(struct device *dev) +{ + uint8_t byte; + int i; + + for(i=0;i<256;i++) { + byte = pci_read_config8(dev, i); + + if((i%16)==0) printk_info("\n%02x:",i); + printk_debug(" %02x",byte); + } + printk_debug("\n"); + +// pci_write_config8(dev, 0x4, byte); + +} +#endif +#if 0 +static void print_mem(void) +{ + int i; + int low_1MB = 0; + for(i=low_1MB;ichip_info; + + switch (pass) { + default: break; +// case CONF_PASS_PRE_CONSOLE: +// case CONF_PASS_PRE_PCI: + case CONF_PASS_POST_PCI: + case CONF_PASS_PRE_BOOT: + if (conf->fixup_scsi) + onboard_scsi_fixup(); +// if (conf->fixup_vga) +// vga_fixup(); + printk_debug("mainboard fixup pass %d done\r\n", + pass); + break; + } + +} +void final_mainboard_fixup(void) +{ +#if 0 + enable_ide_devices(); +#endif +} + +struct chip_control mainboard_tyan_s2882_control = { + .enable= enable, + .name= "Tyan s2882 mainboard " +}; + diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c new file mode 100644 index 0000000000..521cb02584 --- /dev/null +++ b/src/mainboard/tyan/s2882/mptable.c @@ -0,0 +1,140 @@ +#include +#include +#include +#include +#include + +void *smp_write_config_table(void *v, unsigned long * processor_map) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "TYAN "; + static const char productid[12] = "S2882 "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc, processor_map); + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + dev = dev_find_slot(0, PCI_DEVFN(0x1,1)); + if (dev) { + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x11, base); + } + dev = dev_find_slot(0, PCI_DEVFN(0x2,1)); + if (dev) { + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x11, base); + } + } + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xf, 0x2, 0xf); + +//??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1f, 0x2, 0x13); + + +//On Board AMD USB + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13); + +//On Board ATI Display Adapter + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x2, 0x12); +#if 0 +//Slot 5 PCI 32 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x10, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x11, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x12, 0x2, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x13, 0x2, 0x13); // +#endif +//Onboard SI Serial ATA +// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x14, 0x2, 0x11); +#if 0 +//Slot 3 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x20, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x21, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x22, 0x3, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x23, 0x3, 0x2);// + +//Slot 4 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1c, 0x3, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x3, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1e, 0x3, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x3, 0x1);// +#endif +//Onboard adaptec scsi + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x18, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x19, 0x3, 0x1); +//On Board NIC + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x25, 0x3, 0x1); +#if 0 +//Slot 1 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xc, 0x4, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xd, 0x4, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xe, 0x4, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xf, 0x4, 0x3); // + +//Slot 2 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x4, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x4, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1a, 0x4, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1b, 0x4, 0x0);// +#endif +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v, processor_map); +} diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb new file mode 100644 index 0000000000..bdbd7c032f --- /dev/null +++ b/src/mainboard/tyan/s2885/Config.lb @@ -0,0 +1,178 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses USE_NORMAL_IMAGE +uses AMD8111_DEV +uses MAINBOARD +uses ARCH +# +# +### +### Set all of the defaults for an x86 architecture +### +# +# +### +### Build the objects we have code for in this directory. +### +##object mainboard.o +config chip.h +register "fixup_scsi" = "1" +register "fixup_vga" = "1" + +driver mainboard.o +driver broadcom_nic.o +driver ti_firewire.o +driver adaptec_scsi.o +driver si_sata.o +driver intel_nic.o +object static_devices.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +# +arch i386 end +#cpu k8 end +# +### +### Build our 16 bit and 32 bit linuxBIOS entry code +### +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript /cpu/i386/entry16.lds +ldscript /cpu/i386/entry32.lds +# +### +### Build our reset vector (This is where linuxBIOS is entered) +### +if USE_FALLBACK_IMAGE + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds +else +# print "NO FALLBACK USED!" +end + +if USE_NORMAL_IMAGE + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds +end +# +#### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc +# +### +### Include an id string (For safe flashing) +### +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +# +#### +#### This is the early phase of linuxBIOS startup +#### Things are delicate and we test to see if we should +#### failover to another image. +#### +#option MAX_REBOOT_CNT=2 +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +end +# +### +### Setup our mtrrs +### +mainboardinit cpu/k8/earlymtrr.inc +### +### Only the bootstrap cpu makes it here. +### Failover if we need to +### +# +if USE_FALLBACK_IMAGE + mainboardinit ./failover.inc +# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc +end + +# +# +### +### Setup the serial port +### +#mainboardinit superiowinbond/w83627hf/setup_serial.inc +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc +# +#### +#### O.k. We aren't just an intermediary anymore! +#### +# +### +### When debugging disable the watchdog timer +### +##option MAXIMUM_CONSOLE_LOGLEVEL=7 +#default MAXIMUM_CONSOLE_LOGLEVEL=7 +#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) +#if DISABLE_WATCHDOG +# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc +#end +# +#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end +# +### +### Romcc output +### +#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" +#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" +#mainboardinit .failover.inc + +makerule ./failover.E + depends "$(MAINBOARD)/failover.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" +end + +makerule ./failover.inc + depends "./romcc ./failover.E" + action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" +end +makerule ./auto.inc + depends "./romcc ./auto.E" + action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" +# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" +end +mainboardinit cpu/k8/enable_mmx_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/k8/disable_mmx_sse.inc +# +### +### Setup RAM +### +#mainboardinit ram/ramtest.inc +#mainboardinit southbridge/amd/amd8111/smbus.inc +#mainboardinit sdram/generic_dump_spd.inc +# +### +### Include the secondary Configuration files +### +northbridge amd/amdk8 +end +southbridge amd/amd8111 "amd8111" +end +southbridge amd/amd8131 "amd8131" +end +southbridge amd/amd8151 "amd8151" +end +#mainboardinit archi386/smp/secondary.inc +#superio NSC/pc87360 +# register "com1" = "{1}" +# register "lpt" = "{1}" +#end +dir /pc80 +##dir /src/superio/winbond/w83627hf +dir /cpu/k8 +cpu k8 "cpu0" + register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}" + register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}" +end + +cpu k8 "cpu1" +end diff --git a/src/mainboard/tyan/s2885/VERSION b/src/mainboard/tyan/s2885/VERSION new file mode 100644 index 0000000000..cd5ac039d6 --- /dev/null +++ b/src/mainboard/tyan/s2885/VERSION @@ -0,0 +1 @@ +2.0 diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c new file mode 100644 index 0000000000..c494ca0985 --- /dev/null +++ b/src/mainboard/tyan/s2885/auto.c @@ -0,0 +1,213 @@ +#define ASSEMBLY 1 +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/k8/apic_timer.c" +#include "lib/delay.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "debug.c" + +static void memreset_setup(void) +{ + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // BY LYH 28->16 0<<0 --> 1<<0 + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); // BY LYH 29->17 +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + udelay(800); + /* Set memreset_high */ +// outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); // BY LYH 28->17 + udelay(90); +} + +static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) +{ + /* Routing Table Node i + * + * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c + * i: 0, 1, 2, 3, 4, 5, 6, 7 + * + * [ 0: 3] Request Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + * [11: 8] Response Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + * [19:16] Broadcast route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + */ + + uint32_t ret=0x00010101; /* default row entry */ + + static const unsigned int rows_2p[2][2] = { + { 0x00050101, 0x00010404 }, + { 0x00010404, 0x00050101 } + }; + + if(maxnodes>2) { + print_debug("this mainboard is only designed for 2 cpus\r\n"); + maxnodes=2; + } + + + if (!(node>=maxnodes || row>=maxnodes)) { + ret=rows_2p[node][row]; + } + + return ret; +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/cpu_ldtstop.c" +#include "southbridge/amd/amd8111/amd8111_ldtstop.c" + +#include "northbridge/amd/amdk8/raminit.1.c" +#include "northbridge/amd/amdk8/coherent_ht.1.c" +#include "sdram/generic_sdram.c" + +static void enable_lapic(void) +{ + msr_t msr; + msr = rdmsr(0x1b); + msr.hi &= 0xffffff00; + msr.lo &= 0x000007ff; + msr.lo |= APIC_DEFAULT_BASE | (1 << 11); + wrmsr(0x1b, msr); +} + +static void stop_this_cpu(void) +{ + unsigned apicid; + apicid = apic_read(APIC_ID) >> 24; + + /* Send an APIC INIT to myself */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); + + /* Deassert the APIC INIT */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); + + /* If I haven't halted spin forever */ + for(;;) { + hlt(); + } +} +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) +static void main(void) +{ + /* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ + static const struct mem_controller cpu[] = { +#if FIRST_CPU + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + }, +#endif +#if SECOND_CPU + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + }, +#endif + }; + if (cpu_init_detected()) { + asm("jmp __cpu_reset"); + } + enable_lapic(); + init_timer(); + if (!boot_cpu() ) { + notify_bsp_ap_is_stopped(); + stop_this_cpu(); + } + uart_init(); + console_init(); + setup_default_resource_map(); + setup_coherent_ht_domain(); + enumerate_ht_chain(0); + //setup_resource_map_x(); + //enumerate_ht_chain(0); + distinguish_cpu_resets(0); + +#if 0 + print_pci_devices(); +#endif + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + +#if 1 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 1)); +#endif + + /* Check all of memory */ +#if 0 + msr_t msr; + msr = rdmsr(TOP_MEM2); + print_debug("TOP_MEM2: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); +#endif +/* +#if 0 + ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#else +#if TOTAL_CPUS < 2 + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x00100000); +#else + // Check 16MB of memory @ 2GB + ram_check(0x80000000, 0x80100000); +#endif +#endif +*/ +} diff --git a/src/mainboard/tyan/s2885/chip.h b/src/mainboard/tyan/s2885/chip.h new file mode 100644 index 0000000000..75251c70b6 --- /dev/null +++ b/src/mainboard/tyan/s2885/chip.h @@ -0,0 +1,6 @@ +extern struct chip_control mainboard_tyan_s2885_control; + +struct mainboard_tyan_s2885_config { + int fixup_scsi; + int fixup_vga; +}; diff --git a/src/mainboard/tyan/s2885/cmos.layout b/src/mainboard/tyan/s2885/cmos.layout new file mode 100644 index 0000000000..5ba4c032c1 --- /dev/null +++ b/src/mainboard/tyan/s2885/cmos.layout @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + diff --git a/src/mainboard/tyan/s2885/failover.c b/src/mainboard/tyan/s2885/failover.c new file mode 100644 index 0000000000..8b8bcb8b12 --- /dev/null +++ b/src/mainboard/tyan/s2885/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include +#include +#include +#include +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" +#if 0 +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#endif +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +static void main(void) +{ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ +#if 0 + uart_init(); + console_init(); +#endif + enumerate_ht_chain(0); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a cpu reset? */ + if (cpu_init_detected()) { + if (last_boot_normal()) { + asm("jmp __normal_image"); + } else { + asm("jmp __cpu_reset"); + } + } + /* Is this a secondary cpu? */ + else if (!boot_cpu() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + asm("jmp __normal_image"); + } +} diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c new file mode 100644 index 0000000000..607774967f --- /dev/null +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -0,0 +1,35 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*11, /* there can be total 11 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x3b, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, + {0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, + {0x5,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x6, 0}, + {0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, + {0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, + {0x1,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, + {0x1,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, + {0x3,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, + {0x1,0x48, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + {0x3,0x58, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x3,0x60, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + } +}; diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c new file mode 100644 index 0000000000..af8c1ad479 --- /dev/null +++ b/src/mainboard/tyan/s2885/mainboard.c @@ -0,0 +1,174 @@ +#include +#include +#include +#include +#include +#include +#include "chip.h" +//#include +//#include "lsi_scsi.c" +unsigned long initial_apicid[MAX_CPUS] = +{ + 0,1 +}; +#if 0 +static void fixup_lsi_53c1030(struct device *pdev) +{ +// uint8_t byte; + uint16_t word; + + byte = 1; + pci_write_config8(pdev, 0xff, byte); + // Set the device id +// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030); + // Set the subsytem vendor id +// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN); + word = 0x10f1; + pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word); + // Set the subsytem id + word = 0x2880; + pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word); + // Disable writes to the device id + byte = 0; + pci_write_config8(pdev, 0xff, byte); + +// lsi_scsi_init(pdev); + +} +#endif +//extern static void lsi_scsi_init(struct device *dev); +#if 1 +static void print_pci_regs(struct device *dev) +{ + uint8_t byte; + int i; + + for(i=0;i<256;i++) { + byte = pci_read_config8(dev, i); + + if((i%16)==0) printk_info("\n%02x:",i); + printk_debug(" %02x",byte); + } + printk_debug("\n"); + +// pci_write_config8(dev, 0x4, byte); + +} +#endif +#if 0 +static void print_mem(void) +{ + int i; + int low_1MB = 0; + for(i=low_1MB;ichip_info; + + switch (pass) { + default: break; +// case CONF_PASS_PRE_CONSOLE: +// case CONF_PASS_PRE_PCI: +// case CONF_PASS_POST_PCI: + case CONF_PASS_PRE_BOOT: + if (conf->fixup_scsi) + onboard_scsi_fixup(); +// if (conf->fixup_vga) +// vga_fixup(); + printk_debug("mainboard fixup pass %d done\r\n", + pass); + break; + } + +} +void final_mainboard_fixup(void) +{ +#if 0 + enable_ide_devices(); +#endif +} + +struct chip_control mainboard_tyan_s2885_control = { + .enable= enable, + .name= "Tyan s2885 mainboard " +}; + diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c new file mode 100644 index 0000000000..fa8aa9ac08 --- /dev/null +++ b/src/mainboard/tyan/s2885/mptable.c @@ -0,0 +1,146 @@ +#include +#include +#include +#include +#include + +void *smp_write_config_table(void *v, unsigned long * processor_map) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "TYAN "; + static const char productid[12] = "S2885 "; + struct mp_config_table *mc; + unsigned char isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc, processor_map); + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); +#if 1 + isa_bus = 6; + smp_write_bus(mc, 4, "PCI "); //8151 1022/7454 1022/7455 + smp_write_bus(mc, 5, "PCI "); //Bridge +#else + isa_bus = 4; +#endif + smp_write_bus(mc, isa_bus, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + dev = dev_find_slot(0, PCI_DEVFN(0x1,1)); + if (dev) { + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x11, base); + } + dev = dev_find_slot(0, PCI_DEVFN(0x2,1)); + if (dev) { + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x11, base); + } + } + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x5, 0x2, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0xf, 0x2, 0xf); +//??? What + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1f, 0x2, 0x13); +//Onboard AMD AC97 Audio + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1d, 0x2, 0x11); +// Onboard AMD USB + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13); + +// AGP Display Adapter + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x0, 0x2, 0x10); + +// Onboard Serial ATA + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x2c, 0x2, 0x11); +//Onboard Firewire + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x30, 0x2, 0x13); +//Onboard Broadcom NIC + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0); + +//Slot 5 PCI 32 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x28, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x29, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x2a, 0x2, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x2b, 0x2, 0x13); // + +//Slot 3 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x20, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x21, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x22, 0x3, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x23, 0x3, 0x2);// + +//Slot 4 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1c, 0x3, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x3, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1e, 0x3, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x3, 0x1);// + +//Slot 1 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xc, 0x4, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xd, 0x4, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xe, 0x4, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xf, 0x4, 0x3); // + +//Slot 2 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x4, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x4, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1a, 0x4, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1b, 0x4, 0x0);// + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v, processor_map); +} diff --git a/src/mainboard/tyan/s2885/ti_firewire.c b/src/mainboard/tyan/s2885/ti_firewire.c new file mode 100644 index 0000000000..be6cec2f8e --- /dev/null +++ b/src/mainboard/tyan/s2885/ti_firewire.c @@ -0,0 +1,44 @@ +/* Copyright 2003 Tyan */ + +/* Author: Yinghai Lu + * + */ + + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +static void ti_firewire_init(struct device *dev) +{ + uint16_t word; + + word = pci_read_config16(dev, 0x4); + word |= ((1 << 2) |(1<<4)); // Command: 3--> 17 + pci_write_config16(dev, 0x4, word); + + printk_debug("TI_FIREWIRE_FIXUP: done \n"); + +} + +static struct device_operations ti_firewire_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .init = ti_firewire_init, + .scan_bus = 0, +}; + +static struct pci_driver ti_firewire_driver __pci_driver = { + .ops = &ti_firewire_ops, + .vendor = 0x104c, + .device = 0x8023, +}; + diff --git a/src/southbridge/amd/amd8151/Config.lb b/src/southbridge/amd/amd8151/Config.lb new file mode 100644 index 0000000000..00a91b6498 --- /dev/null +++ b/src/southbridge/amd/amd8151/Config.lb @@ -0,0 +1 @@ +driver amd8151_agp3.o diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c new file mode 100644 index 0000000000..b7862feff9 --- /dev/null +++ b/src/southbridge/amd/amd8151/amd8151_agp3.c @@ -0,0 +1,75 @@ +/* + * Copyright 2003 Tyan + * + * Author: Yinghai Lu + */ +#include +#include +#include +#include +#include + +static void agp3bridge_init(device_t dev) +{ + uint32_t dword; + + dword = pci_read_config8(dev, 0x04); + dword |= 0x07; + pci_write_config8(dev, 0x04, dword); + + return; +} + +static struct device_operations agp3bridge_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .init = agp3bridge_init, + .scan_bus = pci_scan_bridge, +}; + +static struct pci_driver agp3bridge_driver __pci_driver = { + .ops = &agp3bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7455, +}; + + +static void agp3dev_enable(device_t dev) +{ + uint32_t value; + + // AGP enable + value = pci_read_config32(dev, 0xa8); + value |= (1<<8); + pci_write_config32(dev, 0xa8, value); + + // linkA 8bit-->16bit + value = pci_read_config32(dev, 0xc4); + value |= (11<<24); + pci_write_config32(dev, 0xc4, value); + + // linkA 200-->600 + value = pci_read_config32(dev, 0xcc); + value |= (4<<8); + pci_write_config32(dev, 0xcc, value); + + + value = pci_read_config32(dev, 0x4); + value |= 6; + pci_write_config32(dev, 0x4, value); +} + +static struct device_operations agp3dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .init = 0, + .scan_bus = 0, + .enable = agp3dev_enable, +}; + +static struct pci_driver agp3dev_driver __pci_driver = { + .ops = &agp3dev_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7454, + +}; diff --git a/targets/tyan/s2880/Config.lb b/targets/tyan/s2880/Config.lb index bce3762f5b..42294f396d 100644 --- a/targets/tyan/s2880/Config.lb +++ b/targets/tyan/s2880/Config.lb @@ -32,7 +32,7 @@ uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAX_CPUS -uses MEMORY_HOLE +#uses MEMORY_HOLE uses PAYLOAD_SIZE uses _RAMBASE uses _ROMBASE @@ -49,6 +49,27 @@ uses USE_NORMAL_IMAGE uses USE_OPTION_TABLE uses HAVE_OPTION_TABLE uses CONFIG_CHIP_CONFIGURE + +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses DEBUG +uses CONFIG_MAX_CPUS +uses CONFIG_LOGICAL_CPUS +uses MAX_PHYSICAL_CPUS +uses LINUXBIOS_EXTRA_VERSION +uses XIP_ROM_SIZE +uses XIP_ROM_BASE + +uses CONFIG_VGABIOS +uses CONFIG_REALMODE_IDT +uses CONFIG_PCIBIOS +uses VGABIOS_START +uses SCSIFW_START + +# +#uses CONFIG_LSI_SCSI_FW_FIXUP option HAVE_OPTION_TABLE=1 option HAVE_MP_TABLE=1 @@ -61,9 +82,19 @@ option k7=1 option k8=1 option ROM_SIZE=524288 +#option CONFIG_VGABIOS=1 +#option CONFIG_REALMODE_IDT=1 +#option CONFIG_PCIBIOS=1 +#option VGABIOS_START=0xfff8c000 +option SCSIFW_START=0xfff80000 + + +option HAVE_FALLBACK_BOOT=1 + # use the new chip configure code. option CONFIG_CHIP_CONFIGURE=1 +#option CONFIG_LSI_SCSI_FW_FIXUP=1 ### Customize our winbond superio chip for this motherboard @@ -82,7 +113,10 @@ option IRQ_SLOT_COUNT=13 ### Only worry about 2 micro processors ### option CONFIG_SMP=1 +option CONFIG_MAX_CPUS=2 option MAX_CPUS=2 +option CONFIG_LOGICAL_CPUS=0 +option MAX_PHYSICAL_CPUS=2 # ### ### Build code to setup a generic IOAPIC @@ -98,7 +132,7 @@ option CONFIG_IOAPIC=1 ### CPU identification depends on only variable MTRRs ### being enabled. ### -option MEMORY_HOLE=0 +#option MEMORY_HOLE=0 # ### ### Enable both fixed and variable MTRRS @@ -112,8 +146,8 @@ option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 ### ### Clean up the motherboard id strings ### -#option MAINBOARD_PART_NUMBER="Solo7" -#option MAINBOARD_VENDOR="AMD" +option MAINBOARD_PART_NUMBER="S2880" +option MAINBOARD_VENDOR="Tyan" # ### ### Call the final_mainboard_fixup function @@ -125,71 +159,108 @@ option FINAL_MAINBOARD_FIXUP=1 ### (linuxBIOS plus bootloader) will live in the boot rom chip. ### #option FALLBACK_SIZE=524288 +option FALLBACK_SIZE=98304 + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +option ROM_IMAGE_SIZE=65536 + + ### ### Compute where this copy of linuxBIOS will start in the boot rom ### # ### -### Compute a range of ROM that can cached to speed up linuxBIOS, -### execution speed. -### -##expr XIP_ROM_SIZE = 65536 -##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE -##option XIP_ROM_SIZE=65536 -##option XIP_ROM_BASE=0xffff0000 -# -## XIP_ROM_SIZE && XIP_ROM_BASE values that work. -##option XIP_ROM_SIZE=0x8000 -##option XIP_ROM_BASE=0xffff8000 -## We don't use compressed image -option CONFIG_COMPRESS=0 +## We do use compressed image +option CONFIG_COMPRESS=1 option USE_ELF_BOOT=1 -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -option ROM_IMAGE_SIZE=65536 + +option CONFIG_CONSOLE_SERIAL8250=1 +option TTYS0_BAUD=115200 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +option DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +option MAXIMUM_CONSOLE_LOGLEVEL=9 + +option DEBUG=1 + +option AMD8111_DEV=0x5 + +# ## LinuxBIOS C code runs at this location in RAM -option _RAMBASE=0x00100000 +option _RAMBASE=0x004000 ## ## Use a 64K stack ## -option STACK_SIZE=0x10000 +option STACK_SIZE=0x2000 ## ## Use a 64K heap ## -option HEAP_SIZE=0x10000 +option HEAP_SIZE=0x2000 # ### ### Compute the start location and size size of ### The linuxBIOS bootloader. ### -option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) option CONFIG_ROM_STREAM = 1 -option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) # -# Arima hdama +# romimage "normal" - option USE_FALLBACK_IMAGE=0 +# 48K for SCSI FW + option ROM_SIZE = 475136 +# 48K for SCSI FW and 48K for ATI ROM +# option ROM_SIZE = 425984 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) option ROM_SECTION_OFFSET= 0 + + option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) + option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) + + option XIP_ROM_SIZE = FALLBACK_SIZE + option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + mainboard tyan/s2880 - payload ../eepro100.ebi + payload ../../tg3--ide_disk.zelf end romimage "fallback" + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" option USE_FALLBACK_IMAGE=1 - option HAVE_FALLBACK_BOOT=1 option ROM_SECTION_SIZE = FALLBACK_SIZE option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) + + option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) + option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) + + option XIP_ROM_SIZE = FALLBACK_SIZE + option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + mainboard tyan/s2880 - payload ../eepro100.ebi + payload ../../tg3.zelf end buildrom ROM_SIZE "normal" "fallback" -- cgit v1.2.3