From f9e10f26ba0c35c99a2781fc9c6bddaca385bf3d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 16 Feb 2020 11:28:11 +0100 Subject: Documentation: Remove confusing xyz0 naming convention for Lenovo devices Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge. Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s. Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Patrick Georgi --- Documentation/mainboard/index.md | 4 +- .../mainboard/lenovo/Ivy_Bridge_series.md | 78 ++++++++++++++++++++++ .../mainboard/lenovo/Sandy_Bridge_series.md | 48 +++++++++++++ .../mainboard/lenovo/flashlayout_Ivy_Bridge.svg | 61 +++++++++++++++++ .../mainboard/lenovo/flashlayout_Sandy_Bridge.svg | 52 +++++++++++++++ .../mainboard/lenovo/flashlayout_xx20.svg | 52 --------------- .../mainboard/lenovo/flashlayout_xx30.svg | 61 ----------------- Documentation/mainboard/lenovo/t420.md | 2 +- Documentation/mainboard/lenovo/t430.md | 2 +- Documentation/mainboard/lenovo/t431s.md | 2 +- Documentation/mainboard/lenovo/w530.md | 2 +- Documentation/mainboard/lenovo/x1.md | 2 +- Documentation/mainboard/lenovo/xx20_series.md | 48 ------------- Documentation/mainboard/lenovo/xx30_series.md | 76 --------------------- 14 files changed, 246 insertions(+), 244 deletions(-) create mode 100644 Documentation/mainboard/lenovo/Ivy_Bridge_series.md create mode 100644 Documentation/mainboard/lenovo/Sandy_Bridge_series.md create mode 100644 Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg create mode 100644 Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg delete mode 100644 Documentation/mainboard/lenovo/flashlayout_xx20.svg delete mode 100644 Documentation/mainboard/lenovo/flashlayout_xx30.svg delete mode 100644 Documentation/mainboard/lenovo/xx20_series.md delete mode 100644 Documentation/mainboard/lenovo/xx30_series.md diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index ce30ee2f1c..3e69119edc 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -82,7 +82,7 @@ The boards in this section are not real mainboards, but emulators. ### Sandy Bridge series - [T420](lenovo/t420.md) -- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) +- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) - [x1](lenovo/x1.md) ### Ivy Bridge series @@ -90,7 +90,7 @@ The boards in this section are not real mainboards, but emulators. - [T430](lenovo/t430.md) - [T530](lenovo/w530.md) - [W530](lenovo/w530.md) -- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) +- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) - [T431s](lenovo/t431s.md) - [Internal flashing](lenovo/ivb_internal_flashing.md) diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md new file mode 100644 index 0000000000..2f83ffa8a8 --- /dev/null +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -0,0 +1,78 @@ +# Lenovo Ivy Bridge series + +This information is valid for all supported models, except T430s and T431s. + +## Flashing coreboot +```eval_rst ++---------------------+--------------------------------+ +| Type | Value | ++=====================+================================+ +| Socketed flash | no | ++---------------------+--------------------------------+ +| Size | 8 MiB + 4MiB | ++---------------------+--------------------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------------+ +| Write protection | No | ++---------------------+--------------------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------------------+ +| Internal flashing | Yes | ++---------------------+--------------------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will permanently brick your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract blobs from vendor firmware. + If you want to flash the whole chip, you need blobs when building + coreboot. +* The *Flash layout* shows that by default 7MiB of space are available for + the use with coreboot. +* In that case you only want to use a part of the BIOS region that must not + exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. +* ROM chip size should be set to 12MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Splitting the coreboot.rom + +To split the coreboot.rom into two images (one for the 8MiB and one for the +4 MiB flash IC), run the following commands: + +```bash +dd of=top.rom bs=1M if=build/coreboot.rom skip=8 +dd of=bottom.rom bs=1M if=build/coreboot.rom count=8 +``` + +That gives one ROM for each flash IC, where *top.rom* is the upper part of the +flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part +of the flash image, that resides on the 8 MiB flash. + +## Dumping a full ROM + +If you flash externally you need to read both flash chips to get two images +(one for the 8MiB and one for the 4 MiB flash IC), and then run the following +command to concatenate the files: + +```bash +cat bottom.rom top.rom > firmware.rom +``` + +## Flash layout +There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and +BIOS region. These two flash ICs appear as a single 12MiB when flashing +internally. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_Ivy_Bridge.svg + diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md new file mode 100644 index 0000000000..0b833f5cc8 --- /dev/null +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -0,0 +1,48 @@ +# Lenovo Sandy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Size | 8 MiB | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will destroy your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract blobs from vendor firmware. + If you want to flash the whole chip, you need blobs when building + coreboot. +* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space + usable by coreboot. +* ROM chip size should be set to 8MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Flash layout +There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_Sandy_Bridge.svg + diff --git a/Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg b/Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg new file mode 100644 index 0000000000..5cc4e4fbaf --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg @@ -0,0 +1,61 @@ + + + + + + + + IFD + + + + + + + ME + + + + + + + BIOS + + + + + + + GBE + + + + 0x000000 + + + 0x001000 + + + 0x003000 + + + 0x500000 + + + 0x800000 + + + + + Flash #0 + + + + + Flash #1 + + + 0xc00000 + + + diff --git a/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg new file mode 100644 index 0000000000..8884ac37ad --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg @@ -0,0 +1,52 @@ + + + + + + + + IFD + + + + + + + ME + + + + + + + BIOS + + + + + + + GBE + + + + 0x000000 + + + 0x001000 + + + 0x003000 + + + 0x500000 + + + 0x800000 + + + + + Flash #0 + + diff --git a/Documentation/mainboard/lenovo/flashlayout_xx20.svg b/Documentation/mainboard/lenovo/flashlayout_xx20.svg deleted file mode 100644 index 8884ac37ad..0000000000 --- a/Documentation/mainboard/lenovo/flashlayout_xx20.svg +++ /dev/null @@ -1,52 +0,0 @@ - - - - - - - - IFD - - - - - - - ME - - - - - - - BIOS - - - - - - - GBE - - - - 0x000000 - - - 0x001000 - - - 0x003000 - - - 0x500000 - - - 0x800000 - - - - - Flash #0 - - diff --git a/Documentation/mainboard/lenovo/flashlayout_xx30.svg b/Documentation/mainboard/lenovo/flashlayout_xx30.svg deleted file mode 100644 index 5cc4e4fbaf..0000000000 --- a/Documentation/mainboard/lenovo/flashlayout_xx30.svg +++ /dev/null @@ -1,61 +0,0 @@ - - - - - - - - IFD - - - - - - - ME - - - - - - - BIOS - - - - - - - GBE - - - - 0x000000 - - - 0x001000 - - - 0x003000 - - - 0x500000 - - - 0x800000 - - - - - Flash #0 - - - - - Flash #1 - - - 0xc00000 - - - diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 831cb58765..40665b4db9 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -22,4 +22,4 @@ For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md index 787246f4d4..1ef4460f5c 100644 --- a/Documentation/mainboard/lenovo/t430.md +++ b/Documentation/mainboard/lenovo/t430.md @@ -12,4 +12,4 @@ For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md index 146e1c12a3..48315a2459 100644 --- a/Documentation/mainboard/lenovo/t431s.md +++ b/Documentation/mainboard/lenovo/t431s.md @@ -39,4 +39,4 @@ inteltool, and replace the content of the SPD hex with what is dumped. I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md index f91d9cee6a..3b54303a73 100644 --- a/Documentation/mainboard/lenovo/w530.md +++ b/Documentation/mainboard/lenovo/w530.md @@ -24,4 +24,4 @@ For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and [w530-2]: w530-2.jpg -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md index cb9248a4e4..9758197a02 100644 --- a/Documentation/mainboard/lenovo/x1.md +++ b/Documentation/mainboard/lenovo/x1.md @@ -21,4 +21,4 @@ For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and Steps to access the flash IC are described here [X2xx series]. [X2xx series]: x2xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/xx20_series.md deleted file mode 100644 index 8603853b94..0000000000 --- a/Documentation/mainboard/lenovo/xx20_series.md +++ /dev/null @@ -1,48 +0,0 @@ -# Lenovo Sandy Bridge series - -## Flashing coreboot -```eval_rst -+---------------------+--------------------+ -| Type | Value | -+=====================+====================+ -| Socketed flash | no | -+---------------------+--------------------+ -| Size | 8 MiB | -+---------------------+--------------------+ -| In circuit flashing | Yes | -+---------------------+--------------------+ -| Package | SOIC-8 | -+---------------------+--------------------+ -| Write protection | No | -+---------------------+--------------------+ -| Dual BIOS feature | No | -+---------------------+--------------------+ -| Internal flashing | Yes | -+---------------------+--------------------+ -``` - -## Installation instructions -* Update the EC firmware, as there's no support for EC updates in coreboot. -* Do **NOT** accidently swap pins or power on the board while a SPI flasher - is connected. It will destroy your device. -* It's recommended to only flash the BIOS region. In that case you don't - need to extract blobs from vendor firmware. - If you want to flash the whole chip, you need blobs when building - coreboot. -* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space - usable by coreboot. -* ROM chip size should be set to 8MiB. - -```eval_rst -Please also have a look at :doc:`../../flash_tutorial/index`. -``` - -## Flash layout -There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. -On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS -region. The update is then written into the EC once. - -![][fl] - -[fl]: flashlayout_xx20.svg - diff --git a/Documentation/mainboard/lenovo/xx30_series.md b/Documentation/mainboard/lenovo/xx30_series.md deleted file mode 100644 index ad856057f0..0000000000 --- a/Documentation/mainboard/lenovo/xx30_series.md +++ /dev/null @@ -1,76 +0,0 @@ -# Lenovo Ivy Bridge series - -## Flashing coreboot -```eval_rst -+---------------------+--------------------------------+ -| Type | Value | -+=====================+================================+ -| Socketed flash | no | -+---------------------+--------------------------------+ -| Size | 8 MiB + 4MiB | -+---------------------+--------------------------------+ -| In circuit flashing | Yes | -+---------------------+--------------------------------+ -| Package | SOIC-8 | -+---------------------+--------------------------------+ -| Write protection | No | -+---------------------+--------------------------------+ -| Dual BIOS feature | No | -+---------------------+--------------------------------+ -| Internal flashing | Yes | -+---------------------+--------------------------------+ -``` - -## Installation instructions -* Update the EC firmware, as there's no support for EC updates in coreboot. -* Do **NOT** accidently swap pins or power on the board while a SPI flasher - is connected. It will permanently brick your device. -* It's recommended to only flash the BIOS region. In that case you don't - need to extract blobs from vendor firmware. - If you want to flash the whole chip, you need blobs when building - coreboot. -* The *Flash layout* shows that by default 7MiB of space are available for - the use with coreboot. -* In that case you only want to use a part of the BIOS region that must not - exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. -* ROM chip size should be set to 12MiB. - -```eval_rst -Please also have a look at :doc:`../../flash_tutorial/index`. -``` - -## Splitting the coreboot.rom - -To split the coreboot.rom into two images (one for the 8MiB and one for the -4 MiB flash IC), run the following commands: - -```bash -dd of=top.rom bs=1M if=build/coreboot.rom skip=8 -dd of=bottom.rom bs=1M if=build/coreboot.rom count=8 -``` - -That gives one ROM for each flash IC, where *top.rom* is the upper part of the -flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part -of the flash image, that resides on the 8 MiB flash. - -## Dumping a full ROM - -If you flash externally you need to read both flash chips to get two images -(one for the 8MiB and one for the 4 MiB flash IC), and then run the following -command to concatenate the files: - -```bash -cat bottom.rom top.rom > firmware.rom -``` - -## Flash layout -There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and -BIOS region. These two flash ICs appear as a single 12MiB when flashing -internally. -On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS -region. The update is then written into the EC once. - -![][fl] - -[fl]: flashlayout_xx30.svg - -- cgit v1.2.3