From f9c12cec3750ccf6911eff90e2102eaac28f6092 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 15 Jun 2023 10:59:49 +0200 Subject: soc/amd/common/iommu.c: Make sure iommu is enabled Don't rely on vendorcode to set enable bit on IOMMU. Signed-off-by: Arthur Heymans Signed-off-by: Naresh Solanki Change-Id: I1805a20656b7fb3915f8cc93c618ee074461840f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75829 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Felix Held --- src/soc/amd/common/block/iommu/iommu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index ad1d774baf..78ec881b49 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #define IOMMU_CAP_BASE_LO 0x44 #define IOMMU_CAP_BASE_HI 0x48 +#define IOMMU_ENABLE (1 << 0) static void iommu_read_resources(struct device *dev) { @@ -23,6 +25,17 @@ static void iommu_read_resources(struct device *dev) res->flags = IORESOURCE_MEM; } + +static void iommu_enable_resources(struct device *dev) +{ + uint32_t base = pci_read_config32(dev, IOMMU_CAP_BASE_LO); + base |= IOMMU_ENABLE; + pci_write_config32(dev, IOMMU_CAP_BASE_LO, base); + printk(BIOS_DEBUG, "%s -> mmio enable: %08X", __func__, + pci_read_config32(dev, IOMMU_CAP_BASE_LO)); + pci_dev_enable_resources(dev); +} + #if CONFIG(HAVE_ACPI_TABLES) static const char *iommu_acpi_name(const struct device *dev) { @@ -33,7 +46,7 @@ static const char *iommu_acpi_name(const struct device *dev) struct device_operations amd_iommu_ops = { .read_resources = iommu_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = iommu_enable_resources, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = iommu_acpi_name, -- cgit v1.2.3