From f9891c8b469232cca28f0b12f613274f127748df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 2 Oct 2019 23:29:07 +0300 Subject: kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware. Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/kontron/986lcd-m/romstage.c | 3 --- src/mainboard/roda/rk886ex/romstage.c | 3 --- src/northbridge/intel/i945/early_init.c | 9 --------- src/southbridge/intel/i82801gx/i82801gx.h | 2 -- 4 files changed, 17 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c0e6071301..7fa1b4271e 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -245,9 +245,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# to conventional PCI slot and Firewire. */ - ich7_p2p_secondary_reset(); - ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7949b697b7..f550632d30 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -208,9 +208,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# to cardbus add-on. */ - ich7_p2p_secondary_reset(); - ich7_enable_lpc(); early_superio_config(); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7ed58f67ab..ee10fdccb6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -869,14 +868,6 @@ static void ich7_setup_pci_express(void) pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } -void ich7_p2p_secondary_reset(void) -{ - pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0); - pci_s_assert_secondary_reset(p2p_bridge); - mdelay(200); - pci_s_deassert_secondary_reset(p2p_bridge); -} - void i945_early_initialization(void) { /* Print some chipset specific information */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index fec891982f..d615b403ac 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,8 +39,6 @@ void i82801gx_enable(struct device *dev); #endif -void ich7_p2p_secondary_reset(void); - void enable_smbus(void); #if ENV_ROMSTAGE -- cgit v1.2.3