From f824784a20a23c64bae6c53d4744fbd8a7cb5c22 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Mon, 2 Oct 2017 15:42:04 +0300
Subject: binaryPI: Fix boot regressions
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Fix boot regression after commit

  d4955f0 AGESA: Move API interface under drivers/

Boards were left without cache-as-ram setup code
and appeared completely dead.

Change-Id: I53a58b817310e91566db3fd660a2c41556f3df5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
---
 src/cpu/amd/pi/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index c6d4532dc4..d25215beef 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,6 +18,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
 
 ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
+cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
 romstage-y += romstage.c
 ramstage-y += amd_late_init.c
 endif
-- 
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