From f7092040fd4aba081aad75116c2b9594149d5c66 Mon Sep 17 00:00:00 2001 From: Greg Watson Date: Fri, 13 Jun 2003 22:07:53 +0000 Subject: More FB2 stuff git-svn-id: svn://svn.coreboot.org/coreboot/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/ppc/boot/linuxbios_table.h | 33 +++++ src/arch/ppc/include/arch/io.h | 73 +++++----- src/arch/ppc/include/arch/pciconf.h | 9 ++ src/arch/ppc/lib/pci_ops.c | 148 +++++++++++++++++++++ src/include/cpu/ppc/cpuid.h | 6 + src/mainboard/motorola/sandpoint/flash.h | 2 +- src/mainboard/motorola/sandpoint/flash/amd800.c | 5 +- src/mainboard/motorola/sandpoint/flash/flash.c | 1 - src/mainboard/motorola/sandpoint/nvram/bsp_nvram.c | 2 +- src/mainboard/motorola/sandpoint/nvram/nvram.c | 3 +- src/northbridge/motorola/mpc107/i2c.c | 6 +- src/northbridge/motorola/mpc107/i2c.h | 8 +- src/northbridge/motorola/mpc107/mpc107.c | 33 +++-- src/northbridge/motorola/mpc107/mpc107_smp.c | 6 +- src/pmc/altimus/mpc7410/mpc7410.c | 1 - src/southbridge/winbond/w83c553/w83c553f.c | 3 +- src/superio/NSC/pc97307/superio.c | 4 +- 17 files changed, 267 insertions(+), 76 deletions(-) create mode 100644 src/arch/ppc/boot/linuxbios_table.h create mode 100644 src/arch/ppc/include/arch/pciconf.h create mode 100644 src/arch/ppc/lib/pci_ops.c create mode 100644 src/include/cpu/ppc/cpuid.h diff --git a/src/arch/ppc/boot/linuxbios_table.h b/src/arch/ppc/boot/linuxbios_table.h new file mode 100644 index 0000000000..42c0a07dac --- /dev/null +++ b/src/arch/ppc/boot/linuxbios_table.h @@ -0,0 +1,33 @@ +#ifndef LINUXBIOS_TABLE_H +#define LINUXBIOS_TABLE_H + +#include + +struct mem_range; + +/* This file holds function prototypes for building the linuxbios table. */ +unsigned long write_linuxbios_table( + unsigned long *processor_map, + struct mem_range *ram, + unsigned long low_table_start, unsigned long low_table_end, + unsigned long rom_table_start, unsigned long rom_table_end); + +struct lb_header *lb_table_init(unsigned long addr); +struct lb_record *lb_first_record(struct lb_header *header); +struct lb_record *lb_last_record(struct lb_header *header); +struct lb_record *lb_next_record(struct lb_record *rec); +struct lb_record *lb_new_record(struct lb_header *header); +struct lb_memory *lb_memory(struct lb_header *header); +void lb_memory_range(struct lb_memory *mem, + uint32_t type, unsigned long startk, unsigned long sizek); +struct lb_mainboard *lb_mainboard(struct lb_header *header); +unsigned long lb_table_fini(struct lb_header *header); + +/* Routines to extract part so the linuxBIOS table or information + * from the linuxBIOS table. + */ +struct lb_memory *get_lb_mem(void); + +extern struct cmos_option_table option_table; + +#endif /* LINUXBIOS_TABLE_H */ diff --git a/src/arch/ppc/include/arch/io.h b/src/arch/ppc/include/arch/io.h index f51f14089e..bc68239a83 100644 --- a/src/arch/ppc/include/arch/io.h +++ b/src/arch/ppc/include/arch/io.h @@ -3,7 +3,8 @@ */ #ifndef _PPC_IO_H #define _PPC_IO_H -#include + +#include #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 @@ -21,12 +22,12 @@ #define _IO_BASE 0xfe000000 -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#define readb(addr) in_8((volatile uint8_t *)(addr)) +#define writeb(b,addr) out_8((volatile uint8_t *)(addr), (b)) +#define readw(addr) in_le16((volatile uint16_t *)(addr)) +#define readl(addr) in_le32((volatile uint32_t *)(addr)) +#define writew(b,addr) out_le16((volatile uint16_t *)(addr),(b)) +#define writel(b,addr) out_le32((volatile uint32_t *)(addr),(b)) #define __raw_readb(addr) (*(volatile unsigned char *)(addr)) @@ -42,19 +43,19 @@ * are arrays of bytes, and byte-swapping is not appropriate in * that case. - paulus */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#define insb(port, buf, ns) _insb((uint8_t *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((uint8_t *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((uint32_t *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((uint32_t *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) +#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) +#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) #define inb_p(port) inb((port)) #define outb_p(val, port) outb((val), (port)) @@ -63,26 +64,26 @@ #define inl_p(port) inl((port)) #define outl_p(val, port) outl((val), (port)) -extern void _insb(volatile u8 *port, void *buf, int ns); -extern void _outsb(volatile u8 *port, const void *buf, int ns); -extern void _insw(volatile u16 *port, void *buf, int ns); -extern void _outsw(volatile u16 *port, const void *buf, int ns); -extern void _insl(volatile u32 *port, void *buf, int nl); -extern void _outsl(volatile u32 *port, const void *buf, int nl); -extern void _insw_ns(volatile u16 *port, void *buf, int ns); -extern void _outsw_ns(volatile u16 *port, const void *buf, int ns); -extern void _insl_ns(volatile u32 *port, void *buf, int nl); -extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); +extern void _insb(volatile uint8_t *port, void *buf, int ns); +extern void _outsb(volatile uint8_t *port, const void *buf, int ns); +extern void _insw(volatile uint16_t *port, void *buf, int ns); +extern void _outsw(volatile uint16_t *port, const void *buf, int ns); +extern void _insl(volatile uint32_t *port, void *buf, int nl); +extern void _outsl(volatile uint32_t *port, const void *buf, int nl); +extern void _insw_ns(volatile uint16_t *port, void *buf, int ns); +extern void _outsw_ns(volatile uint16_t *port, const void *buf, int ns); +extern void _insl_ns(volatile uint32_t *port, void *buf, int nl); +extern void _outsl_ns(volatile uint32_t *port, const void *buf, int nl); /* * The *_ns versions below don't do byte-swapping. * Neither do the standard versions now, these are just here * for older code. */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define insw_ns(port, buf, ns) _insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((uint32_t *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((uint32_t *)((port)+_IO_BASE), (buf), (nl)) #define IO_SPACE_LIMIT ~0 @@ -180,9 +181,9 @@ extern inline void out_be32(volatile unsigned *addr, int val) __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } -extern inline void _insw_ns(volatile u16 *port, void *buf, int ns) +extern inline void _insw_ns(volatile uint16_t *port, void *buf, int ns) { - u16 * b = (u16 *)buf; + uint16_t * b = (uint16_t *)buf; while (ns > 0) { *b++ = readw(port); diff --git a/src/arch/ppc/include/arch/pciconf.h b/src/arch/ppc/include/arch/pciconf.h new file mode 100644 index 0000000000..8695ee2294 --- /dev/null +++ b/src/arch/ppc/include/arch/pciconf.h @@ -0,0 +1,9 @@ +#ifndef PCI_CONF_REG_INDEX + +// These are defined in the PCI spec, and hence are theoretically +// inclusive of ANYTHING that uses a PCI bus. +#define PCI_CONF_REG_INDEX 0xcf8 +#define PCI_CONF_REG_DATA 0xcfc +#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) + +#endif diff --git a/src/arch/ppc/lib/pci_ops.c b/src/arch/ppc/lib/pci_ops.c new file mode 100644 index 0000000000..69c9915ad6 --- /dev/null +++ b/src/arch/ppc/lib/pci_ops.c @@ -0,0 +1,148 @@ +#include +#include +#include +#include +#include +#include + +static const struct pci_ops *conf; +struct pci_ops { + uint8_t (*read8) (uint8_t bus, int devfn, int where); + uint16_t (*read16) (uint8_t bus, int devfn, int where); + uint32_t (*read32) (uint8_t bus, int devfn, int where); + int (*write8) (uint8_t bus, int devfn, int where, uint8_t val); + int (*write16) (uint8_t bus, int devfn, int where, uint16_t val); + int (*write32) (uint8_t bus, int devfn, int where, uint32_t val); +}; + +struct pci_ops pci_direct_ppc; + +extern unsigned __pci_config_read_32(unsigned address); +extern unsigned __pci_config_read_16(unsigned address); +extern unsigned __pci_config_read_8(unsigned address); +extern void __pci_config_write_32(unsigned address, unsigned data); +extern void __pci_config_write_16(unsigned address, unsigned short data); +extern void __pci_config_write_8(unsigned address, unsigned char data); + +#define CONFIG_CMD(bus,devfn,where) (bus << 16 | devfn << 8 | where | 0x80000000) + +/* + * Direct access to PCI hardware... + */ + +/* + * Before we decide to use direct hardware access mechanisms, we try to do some + * trivial checks to ensure it at least _seems_ to be working -- we just test + * whether bus 00 contains a host bridge (this is similar to checking + * techniques used in XFree86, but ours should be more reliable since we + * attempt to make use of direct access hints provided by the PCI BIOS). + * + * This should be close to trivial, but it isn't, because there are buggy + * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. + */ +static int pci_sanity_check(const struct pci_ops *o) +{ + uint16_t class, vendor; + uint8_t bus; + int devfn; +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_MOTOROLA 0x1057 + + for (bus = 0, devfn = 0; devfn < 0x100; devfn++) { + class = o->read16(bus, devfn, PCI_CLASS_DEVICE); + vendor = o->read16(bus, devfn, PCI_VENDOR_ID); + if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) || + ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) || + (vendor == PCI_VENDOR_ID_MOTOROLA))) { + return 1; + } + } + + printk_err("PCI: Sanity check failed\n"); + return 0; +} + +uint8_t pci_read_config8(struct device *dev, unsigned where) +{ + return conf->read8(dev->bus->secondary, dev->devfn, where); +} + +uint16_t pci_read_config16(struct device *dev, unsigned where) +{ + return conf->read16(dev->bus->secondary, dev->devfn, where); +} + +uint32_t pci_read_config32(struct device *dev, unsigned where) +{ + return conf->read32(dev->bus->secondary, dev->devfn, where); +} + +void pci_write_config8(struct device *dev, unsigned where, uint8_t val) +{ + conf->write8(dev->bus->secondary, dev->devfn, where, val); +} + +void pci_write_config16(struct device *dev, unsigned where, uint16_t val) +{ + conf->write16(dev->bus->secondary, dev->devfn, where, val); +} + +void pci_write_config32(struct device *dev, unsigned where, uint32_t val) +{ + conf->write32(dev->bus->secondary, dev->devfn, where, val); +} + +/** Set the method to be used for PCI + */ +void pci_set_method(void) +{ + conf = &pci_direct_ppc; + pci_sanity_check(conf); +} + +static uint8_t pci_ppc_read_config8(unsigned char bus, int devfn, int where) +{ + return (uint8_t)__pci_config_read_8(CONFIG_CMD(bus, devfn, where)); +} + +static uint16_t pci_ppc_read_config16(unsigned char bus, int devfn, int where) +{ + return (uint16_t)__pci_config_read_16(CONFIG_CMD(bus, devfn, where)); +} + +static uint32_t pci_ppc_read_config32(unsigned char bus, int devfn, int where) +{ + return (uint32_t)__pci_config_read_32(CONFIG_CMD(bus, devfn, where)); +} + +static int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data) +{ + __pci_config_write_8(CONFIG_CMD(bus, devfn, where), data); + return 0; +} + +static int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data) +{ + __pci_config_write_16(CONFIG_CMD(bus, devfn, where), data); + return 0; +} + +static int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data) +{ + __pci_config_write_32(CONFIG_CMD(bus, devfn, where), data); + return 0; +} + +struct pci_ops pci_direct_ppc = +{ + pci_ppc_read_config8, + pci_ppc_read_config16, + pci_ppc_read_config32, + pci_ppc_write_config8, + pci_ppc_write_config16, + pci_ppc_write_config32 +}; + diff --git a/src/include/cpu/ppc/cpuid.h b/src/include/cpu/ppc/cpuid.h new file mode 100644 index 0000000000..8a497dfd11 --- /dev/null +++ b/src/include/cpu/ppc/cpuid.h @@ -0,0 +1,6 @@ +#ifndef CPU_PPC_CPUID_H +#define CPU_PPC_CPUID_H + +void display_cpuid(void); + +#endif /* CPU_PPC_CPUID_H */ diff --git a/src/mainboard/motorola/sandpoint/flash.h b/src/mainboard/motorola/sandpoint/flash.h index 5ef1c6e19a..bd104a529c 100644 --- a/src/mainboard/motorola/sandpoint/flash.h +++ b/src/mainboard/motorola/sandpoint/flash.h @@ -14,7 +14,7 @@ typedef struct flash_fn int (* erase_all)(void *data); int (* erase)(void *data, unsigned offset, unsigned length); int (* program)(void *data, unsigned offset, const void *source, unsigned length); - u8 ( *read_byte)(void *data, unsigned offset); + uint8_t ( *read_byte)(void *data, unsigned offset); } flash_fn; typedef struct flash_device diff --git a/src/mainboard/motorola/sandpoint/flash/amd800.c b/src/mainboard/motorola/sandpoint/flash/amd800.c index a9064a3aba..607f3d7635 100644 --- a/src/mainboard/motorola/sandpoint/flash/amd800.c +++ b/src/mainboard/motorola/sandpoint/flash/amd800.c @@ -2,7 +2,6 @@ /* Copyright 2000 AG Electronics Ltd. */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */ -#include #include #include #include "../flash.h" @@ -19,7 +18,7 @@ static const char *identify_amd (struct flash_device *flash_device); static int erase_flash_amd800 (void *data, unsigned offset, unsigned length); static int program_flash_amd800 (void *data, unsigned offset, const void *source, unsigned length); -static u8 read_byte_amd800(void *data, unsigned offset); +static uint8_t read_byte_amd800(void *data, unsigned offset); static flash_fn fn_amd800 = { identify_amd, @@ -221,7 +220,7 @@ int program_flash_amd800 (void *data, unsigned offset, const void *source, return 0; } -u8 read_byte_amd800 (void *data, unsigned offset) +uint8_t read_byte_amd800 (void *data, unsigned offset) { struct data_amd800 *d800 = data; volatile unsigned char *flash = (volatile unsigned char *) d800->base; diff --git a/src/mainboard/motorola/sandpoint/flash/flash.c b/src/mainboard/motorola/sandpoint/flash/flash.c index be0d40cefe..8db0f6aa57 100644 --- a/src/mainboard/motorola/sandpoint/flash/flash.c +++ b/src/mainboard/motorola/sandpoint/flash/flash.c @@ -2,7 +2,6 @@ /* Copyright 2000 AG Electronics Ltd. */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */ -#include #include #include #include diff --git a/src/mainboard/motorola/sandpoint/nvram/bsp_nvram.c b/src/mainboard/motorola/sandpoint/nvram/bsp_nvram.c index bf5a81c812..7208b18d55 100644 --- a/src/mainboard/motorola/sandpoint/nvram/bsp_nvram.c +++ b/src/mainboard/motorola/sandpoint/nvram/bsp_nvram.c @@ -49,6 +49,6 @@ static int bsp_write_byte(struct nvram_device *data, unsigned offset, unsigned c } nvram_device bsp_nvram = { - bsp_size, bsp_read_block, bsp_write_byte, NULL, NULL + bsp_size, bsp_read_block, bsp_write_byte, 0, 0 }; diff --git a/src/mainboard/motorola/sandpoint/nvram/nvram.c b/src/mainboard/motorola/sandpoint/nvram/nvram.c index 13735748b7..45ca3f26e9 100644 --- a/src/mainboard/motorola/sandpoint/nvram/nvram.c +++ b/src/mainboard/motorola/sandpoint/nvram/nvram.c @@ -2,7 +2,6 @@ /* Copyright 2000 AG Electronics Ltd. */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */ -#include #include #include #include "../nvram.h" @@ -20,7 +19,7 @@ static nvram_device *nvram_dev = 0; static unsigned char *nvram_buffer = 0; static unsigned nvram_size = 0; -static u8 nvram_csum = 0; +static uint8_t nvram_csum = 0; #define NVRAM_INVALID (! nvram_dev) static void update_device(unsigned i, unsigned char data) diff --git a/src/northbridge/motorola/mpc107/i2c.c b/src/northbridge/motorola/mpc107/i2c.c index 4ead02331b..5f06a5136f 100644 --- a/src/northbridge/motorola/mpc107/i2c.c +++ b/src/northbridge/motorola/mpc107/i2c.c @@ -18,8 +18,8 @@ * MA 02111-1307 USA */ -#include #include +#include #include #include "i2c.h" @@ -80,7 +80,7 @@ void i2c_stop(struct i2c_bus *bus) } int i2c_master_write(struct i2c_bus *bus, int target, int address, - const u8 *data, int length) + const uint8_t *data, int length) { if (! bus) bus = first_i2c; @@ -89,7 +89,7 @@ int i2c_master_write(struct i2c_bus *bus, int target, int address, } int i2c_master_read(struct i2c_bus *bus, int target, int address, - u8 *data, int length) + uint8_t *data, int length) { if (! bus) bus = first_i2c; diff --git a/src/northbridge/motorola/mpc107/i2c.h b/src/northbridge/motorola/mpc107/i2c.h index 868c94a082..c335a6f9ee 100644 --- a/src/northbridge/motorola/mpc107/i2c.h +++ b/src/northbridge/motorola/mpc107/i2c.h @@ -28,9 +28,9 @@ typedef struct i2c_fn void (* start)(struct i2c_bus *bus); void (* stop)(struct i2c_bus *bus); int (* master_write)(struct i2c_bus *bus, int target, int address, - const u8 *data, int length); + const uint8_t *data, int length); int (* master_read)(struct i2c_bus *bus, int target, int address, - u8 *data, int length); + uint8_t *data, int length); } i2c_fn; typedef struct i2c_bus @@ -47,9 +47,9 @@ int register_i2c_bus(const i2c_fn *fn, char *tag, void *data); void i2c_start(struct i2c_bus *bus); void i2c_stop(struct i2c_bus *bus); int i2c_master_write(struct i2c_bus *bus, int target, int address, - const u8 *data, int length); + const uint8_t *data, int length); int i2c_master_read(struct i2c_bus *bus, int target, int address, - u8 *data, int length); + uint8_t *data, int length); void init_i2c_nvram(const char *i2c_tag); extern i2c_fn mpc107_i2c_fn; diff --git a/src/northbridge/motorola/mpc107/mpc107.c b/src/northbridge/motorola/mpc107/mpc107.c index ed02fb73d1..e0460ba90a 100644 --- a/src/northbridge/motorola/mpc107/mpc107.c +++ b/src/northbridge/motorola/mpc107/mpc107.c @@ -17,12 +17,11 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#include #include #include -#include #include #include -#include #include #include #include @@ -88,16 +87,16 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real) unsigned acttorw, acttopre; unsigned pretoact, bstopre; enum sdram_error_detect error_detect; - u32 mccr1; - u32 mccr2; - u32 mccr3; - u32 mccr4; - u8 bank_enable; - u32 memstart1, memstart2; - u32 extmemstart1, extmemstart2; - u32 memend1, memend2; - u32 extmemend1, extmemend2; - u32 address; + uint32_t mccr1; + uint32_t mccr2; + uint32_t mccr3; + uint32_t mccr4; + uint8_t bank_enable; + uint32_t memstart1, memstart2; + uint32_t extmemstart1, extmemstart2; + uint32_t memend1, memend2; + uint32_t extmemend1, extmemend2; + uint32_t address; struct device *dev; if ((dev = dev_find_slot(0, 0)) == NULL ) @@ -248,7 +247,7 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real) bank_enable = 0; for (i = 0; i < no_banks; i++) { if (! ignore[i]) { - u32 end = address + bank[i].size - 1; + uint32_t end = address + bank[i].size - 1; bank_enable |= 1 << i; if (i < 4) { memstart1 |= ((address >> 20) & 0xff) << (8 * i); @@ -290,7 +289,7 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real) static int i2c_wait(unsigned timeout, int writing) { - u32 x; + uint32_t x; while (((x = readl(MPC107_BASE + MPC107_I2CSR)) & (MPC107_I2C_CSR_MCF | MPC107_I2C_CSR_MIF)) != (MPC107_I2C_CSR_MCF | MPC107_I2C_CSR_MIF)) { if (ticks_since_boot() > timeout) @@ -327,7 +326,7 @@ mpc107_i2c_stop(struct i2c_bus *bus) } static int -mpc107_i2c_byte_write(struct i2c_bus *bus, int target, int address, u8 data) +mpc107_i2c_byte_write(struct i2c_bus *bus, int target, int address, uint8_t data) { unsigned timeout = ticks_since_boot() + 3 * get_hz(); @@ -361,7 +360,7 @@ mpc107_i2c_byte_write(struct i2c_bus *bus, int target, int address, u8 data) } static int -mpc107_i2c_master_write(struct i2c_bus *bus, int target, int address, const u8 *data, int length) +mpc107_i2c_master_write(struct i2c_bus *bus, int target, int address, const uint8_t *data, int length) { unsigned count; for(count = 0; count < length; count++) @@ -376,7 +375,7 @@ mpc107_i2c_master_write(struct i2c_bus *bus, int target, int address, const u8 * static int mpc107_i2c_master_read(struct i2c_bus *bus, int target, int address, - u8 *data, int length) + uint8_t *data, int length) { unsigned timeout = ticks_since_boot() + 3 * get_hz(); unsigned count; diff --git a/src/northbridge/motorola/mpc107/mpc107_smp.c b/src/northbridge/motorola/mpc107/mpc107_smp.c index c23e686334..afdd538fde 100644 --- a/src/northbridge/motorola/mpc107/mpc107_smp.c +++ b/src/northbridge/motorola/mpc107/mpc107_smp.c @@ -1,4 +1,4 @@ -#include +#include #include #include "mpc107.h" @@ -10,10 +10,10 @@ wait_for_other_cpus(void) unsigned long this_processors_id(void) { - u32 pic1; + uint32_t pic1; struct device *dev; - if ((dev = dev_find_slot(0, 0)) == NULL) + if ((dev = dev_find_slot(0, 0)) == 0) return 0; pic1 = pci_read_config32(dev, MPC107_PIC1); diff --git a/src/pmc/altimus/mpc7410/mpc7410.c b/src/pmc/altimus/mpc7410/mpc7410.c index 29f65d796b..cb556b0793 100644 --- a/src/pmc/altimus/mpc7410/mpc7410.c +++ b/src/pmc/altimus/mpc7410/mpc7410.c @@ -4,7 +4,6 @@ #include #include -#include #include #include diff --git a/src/southbridge/winbond/w83c553/w83c553f.c b/src/southbridge/winbond/w83c553/w83c553f.c index daca1c11bb..2d9daaea93 100644 --- a/src/southbridge/winbond/w83c553/w83c553f.c +++ b/src/southbridge/winbond/w83c553/w83c553f.c @@ -27,7 +27,6 @@ * Enabling function 1 (IDE controller of the chip. */ -#include #include #include #include @@ -47,7 +46,7 @@ #define CONFIG_IDE_MAXDEVICE (CONFIG_IDE_MAXBUS*2) #endif -u32 ide_bus_offset[CONFIG_IDE_MAXBUS]; +uint32_t ide_bus_offset[CONFIG_IDE_MAXBUS]; void initialise_pic(void); void initialise_dma(void); diff --git a/src/superio/NSC/pc97307/superio.c b/src/superio/NSC/pc97307/superio.c index 0a04806a8b..99f0eac6a2 100644 --- a/src/superio/NSC/pc97307/superio.c +++ b/src/superio/NSC/pc97307/superio.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #ifndef PNP_INDEX_REG @@ -37,6 +36,7 @@ void sio_enable(void) pnp_output(0x30, 1); /* Activate */ } +#if 0 struct superio_control superio_NSC_pc97307_control = { pre_pci_init: (void *)0, init: (void *)0, @@ -44,4 +44,4 @@ struct superio_control superio_NSC_pc97307_control = { defaultport: SIO_COM1_BASE, name: "NSC 87307" }; - +#endif -- cgit v1.2.3