From f669c81cf47f91ba66c22db15a6ef911e6e15e50 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 16 Jan 2021 14:59:30 +0100 Subject: northbridge/intel/x4x/dq_dqs.c: Remove repeated word Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/49523 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/x4x/dq_dqs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 82dca44f72..4722dfe7a6 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -746,7 +746,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank) * DDR3 uses flyby topology where the clock signal takes a different path * than the data signal, to allow for better signal intergrity. * Therefore the delay on the data signals needs to account for this. - * This is done by by sampleling the the DQS write (tx) signal back over + * This is done by sampleling the DQS write (tx) signal back over * the DQ signal and looking for delay values where the sample transitions * from high to low. * Here the following is done: -- cgit v1.2.3