From f5b993de4fcf9b1153681e64285139e69e2c87cd Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 15 Apr 2024 23:14:56 -0400 Subject: sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN According to datasheet, the enable bit for direct I/O access to GPIO lines is at CR30[3] of LDN 8, not [0] as currently coded. Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/superio/nuvoton/nct6779d/nct6779d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h index 85f4081368..30694ea5c8 100644 --- a/src/superio/nuvoton/nct6779d/nct6779d.h +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -22,7 +22,7 @@ /* virtual LDN for GPIO */ -#define NCT6779D_GPIOBASE ((0 << 8) | NCT6779D_WDT1_GPIO01_V) +#define NCT6779D_GPIOBASE ((3 << 8) | NCT6779D_WDT1_GPIO01_V) #define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT1_GPIO01_V) #define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO12345678_V) -- cgit v1.2.3