From f580d9ffef93243509e84d558e42a8722d0ad6e7 Mon Sep 17 00:00:00 2001
From: Wisley Chen <wisley.chen@quantatw.com>
Date: Wed, 14 Oct 2020 16:25:11 +0800
Subject: mb/google/volteer/elemi: Add memory.c for DDR4
Add new memory.c to support DDR4 memory types.
BUG=b:170604353
TEST=emerge-volteer coreboot chromeos-bootimage
Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
.../google/volteer/variants/elemi/Makefile.inc | 3 +++
.../google/volteer/variants/elemi/memory.c | 31 ++++++++++++++++++++++
2 files changed, 34 insertions(+)
create mode 100644 src/mainboard/google/volteer/variants/elemi/Makefile.inc
create mode 100644 src/mainboard/google/volteer/variants/elemi/memory.c
diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
new file mode 100644
index 0000000000..9064208bff
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c
new file mode 100644
index 0000000000..d3de4be711
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/elemi/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */
+static const struct mb_ddr4_cfg elemi_memcfg = {
+};
+
+static const struct ddr_memory_cfg baseboard_memcfg = {
+ .mem_type = MEMTYPE_DDR4,
+ .ddr4_cfg = &elemi_memcfg
+};
+
+const struct ddr_memory_cfg *variant_memory_params(void)
+{
+ return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_3,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_0,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
--
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