From f2be7d6056631638b6965dec6376c4f75e4d7a86 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Tue, 3 Aug 2021 16:23:08 +0800 Subject: mb/google/brya/variants/gimble: Remove DPTF fan control BUG=b:195378817 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao Change-Id: I84c020e470194072bb796f75f8a1304832504469 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56768 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../google/brya/variants/gimble/overridetree.cb | 28 +--------------------- 1 file changed, 1 insertion(+), 27 deletions(-) diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index e1507ce3e1..b658d20462 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -32,17 +32,7 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM"" register "options.tsr[1].desc" = ""Charger"" # TODO: below values are initial reference values only - ## Active Policy - register "policies.active" = "{ - [0] = { - .target = DPTF_CPU, - .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - } - } - }" + ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), @@ -78,22 +68,6 @@ chip soc/intel/alderlake [2] = { 16, 1000 }, [3] = { 8, 500 } }" - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } - }" - ## Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" device generic 0 on end end end -- cgit v1.2.3