From eef442d0c1d4bab616aaa077d80a56c64cac6f1e Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 12 Jul 2021 15:01:11 +0800 Subject: soc/mediatek/mt8192: initialize DFD DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. Signed-off-by: Rex-BC Chen Change-Id: I39a4391c1d1e832d77b709f8f899bb1c6dcacd69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56797 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/Kconfig | 6 ++++++ src/soc/mediatek/mt8192/Makefile.inc | 1 + src/soc/mediatek/mt8192/dfd.c | 12 ++++++++++++ src/soc/mediatek/mt8192/include/soc/dfd.h | 17 +++++++++++++++++ src/soc/mediatek/mt8192/soc.c | 10 ++++++++++ 5 files changed, 46 insertions(+) create mode 100644 src/soc/mediatek/mt8192/dfd.c create mode 100644 src/soc/mediatek/mt8192/include/soc/dfd.h diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index eb4aab65fe..21dcc7c478 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -63,4 +63,10 @@ config SRCLKEN_RC_SUPPORT This option enables clock buffer remote controller module to control PMIC 26MHz clock output. +config MTK_DFD + bool + default n + help + This option enables DFD (Design for Debug) settings. + endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e5043597d0..5bd88c32a4 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += apusys.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c +ramstage-y += dfd.c ramstage-y += ../common/dpm.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/flash_controller.c diff --git a/src/soc/mediatek/mt8192/dfd.c b/src/soc/mediatek/mt8192/dfd.c new file mode 100644 index 0000000000..4d1b08aab4 --- /dev/null +++ b/src/soc/mediatek/mt8192/dfd.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void dfd_init(void) +{ + printk(BIOS_INFO, "[%s]\n", __func__); + setbits32(dfd_cfg, RESET_ON_KEEP_EN); + dsb(); +} diff --git a/src/soc/mediatek/mt8192/include/soc/dfd.h b/src/soc/mediatek/mt8192/include/soc/dfd.h new file mode 100644 index 0000000000..650e5fd091 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dfd.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_DFD_H +#define SOC_MEDIATEK_MT8192_DFD_H + +#define CPC_FLOW_CTRL_CFG 0x0C53A814 +#define RESET_ON_KEEP_EN BIT(17) + +/* DFD dump address and size need to be the same as defined in Kernel DTS. */ +#define DFD_DUMP_ADDRESS 0x6A000000 +#define DFD_DUMP_SIZE (1 * MiB) + +static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG; + +void dfd_init(void); + +#endif diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 70c5fa32a3..006a212da9 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include #include #include #include @@ -10,6 +12,12 @@ #include #include +void bootmem_platform_add_ranges(void) +{ + if (CONFIG(MTK_DFD)) + bootmem_add_range(DFD_DUMP_ADDRESS, DFD_DUMP_SIZE, BM_MEM_RESERVED); +} + static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); @@ -22,6 +30,8 @@ static void soc_init(struct device *dev) dapc_init(); mcupm_init(); sspm_init(); + if (CONFIG(MTK_DFD)) + dfd_init(); ufs_disable_refclk(); } -- cgit v1.2.3