From ed48dfdc4edd08d4e9641a87839a9904fdd98c13 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Tue, 24 Feb 2015 03:07:02 +0100 Subject: cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens Reviewed-on: http://review.coreboot.org/8658 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/cpu/intel/model_2065x/model_2065x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 454f7be662..702eceb3b3 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -35,6 +35,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_FERR_CAPABILITY 0x1f1 +#define FERR_ENABLE (1 << 0) #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -- cgit v1.2.3