From ed029a9c6cd901a647870d1af5138e4d1b566cb1 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 20 Mar 2023 13:27:34 -0600 Subject: soc/amd/mendocino: Remove 2 unused PCIe functions Mendocino only has 4 PCIe lanes exposed, so there's no need for 6 PCIe functions to control them. These functions just show up as leftover devicetree devices. Signed-off-by: Martin Roth Change-Id: I5b801d82f085d77706b8053a8fc9728101f155e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73853 Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/mendocino/chipset_mendocino.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 2ecb240543..c28c5fc9f6 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -14,8 +14,6 @@ chip soc/amd/mendocino device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A -- cgit v1.2.3