From ecec9474d808f532822091c5a6069f57abc1c81d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 3 Aug 2020 15:44:27 +0200 Subject: nb/intel/x4x: Change signature of `decode_pciebar` Rename it and make it return an int, like other northbridges do. Change-Id: I8bbf28350976547c83e039731d316e0911197d54 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/x4x/acpi.c | 2 +- src/northbridge/intel/x4x/memmap.c | 2 +- src/northbridge/intel/x4x/northbridge.c | 2 +- src/northbridge/intel/x4x/x4x.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 57173fd156..c70007621b 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -12,7 +12,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar = 0; u32 length = 0; - if (!decode_pciebar(&pciexbar, &length)) + if (!decode_pcie_bar(&pciexbar, &length)) return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e2be..6d40fafc67 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -57,7 +57,7 @@ u32 decode_tseg_size(const u32 esmramc) } } -u8 decode_pciebar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 9c32dae275..99b1f21843 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -111,7 +111,7 @@ static void mch_domain_read_resources(struct device *dev) top32memk - (DEFAULT_HECIBAR >> 10), IORESOURCE_RESERVE); - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, index++, pcie_config_base >> 10, diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 133f31d174..bb51c60fd8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -331,7 +331,7 @@ void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); -u8 decode_pciebar(u32 *const base, u32 *const len); +int decode_pcie_bar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); void do_raminit(struct sysinfo *, int fast_boot); void rcven(struct sysinfo *s); -- cgit v1.2.3