From e8e2e3e00d6a4184419c52c3395c72ad4ba95eac Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 12 Jul 2020 23:11:50 +0200 Subject: sb/intel/i82371eb: Declare reset register in FADT According to Intel Order Number 290562 (PIIX4 datasheet), 0xcf9 is the reset register, and setting bits 1 and 2 will result in a hard reset. Change-Id: Id5ada6a10b2269d51908c6a5fd7745ef6c33a29a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43385 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82371eb/fadt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index fb3b49eb49..5a3326bc8f 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -103,15 +103,15 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) * 18 FORCE_APIC_CLUSTER_MODEL * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE */ - fadt->flags = 0xa5; + fadt->flags = 0xa5 | ACPI_FADT_RESET_REGISTER; - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; -- cgit v1.2.3