From e85e0f57acf1b1dfe86b54689cf89659bfd94a54 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 25 Jan 2018 17:39:06 -0800 Subject: mainboard/google/meowth: Turn on DBC over USB3.0 Intel DCI (direct connect interface) allows debug Intel target using USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0 only. BUG=None TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot image. Using DAL to halt/run CPU. Change-Id: I39e68dabfcb9e659733019334299e562eee3681d Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/23446 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 20654e39d8..c0e4ac3317 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -6,6 +6,9 @@ chip soc/intel/cannonlake register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" + # Debug Option, set to DBC over USB 3.0 port only + register "DebugConsent" = "DebugConsent_USB3_DBC" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE -- cgit v1.2.3