From e585f5b5cc29b006c551c746fb0bfb5fc69ec358 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Wed, 29 Apr 2020 09:43:32 +0200
Subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/soc/intel/icelake/bootblock/pch.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 402fb9aa34..6ebf9101b3 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -41,22 +41,21 @@
 static void soc_config_pwrmbase(void)
 {
 	uint32_t reg32;
+	uint16_t reg16;
 
 	/*
 	 * Assign Resources to PWRMBASE
 	 * Clear BIT 1-2  Command Register
 	 */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+	reg16 &= ~(PCI_COMMAND_MEMORY);
+	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
 
 	/* Program PWRM Base */
 	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
 
 	/* Enable Bus Master and MMIO Space */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MEMORY;
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 	/* Enable PWRM in PMC */
 	reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
-- 
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