From e50bb8fc9efe25edf1ab27c7b6a88dfb7293ce06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 2 Nov 2021 18:16:32 +0200 Subject: ChromeOS: Add legacy mainboard_ec_running_ro() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Motivation is to have mainboard_chromeos_acpi_generate() do nothing else than fill ACPI \OIPG package. Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Julius Werner --- src/include/bootmode.h | 3 +++ src/mainboard/google/butterfly/chromeos.c | 16 +++++++++------- src/mainboard/google/parrot/chromeos.c | 5 +---- src/mainboard/google/stout/chromeos.c | 11 ++++++----- src/mainboard/samsung/lumpy/chromeos.c | 8 +++++--- src/vendorcode/google/chromeos/chromeos.h | 1 - src/vendorcode/google/chromeos/gnvs.c | 19 ++++++++++--------- 7 files changed, 34 insertions(+), 29 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index da2dbf6565..e2d1cb9a94 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -3,6 +3,8 @@ #ifndef __BOOTMODE_H__ #define __BOOTMODE_H__ +#include + /* functions implemented per mainboard: */ void init_bootmode_straps(void); int get_write_protect_state(void); @@ -12,6 +14,7 @@ int clear_recovery_mode_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); int get_ec_is_trusted(void); +bool mainboard_ec_running_ro(void); /* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index a7d56aee4a..fb249d4def 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -48,6 +48,15 @@ int get_recovery_mode_switch(void) return 0; } +bool mainboard_ec_running_ro(void) +{ + // TODO: MLR + // The firmware read/write status is a "virtual" switch and + // will be handled elsewhere. Until then hard-code to + // read/write instead of read-only for developer mode. + return false; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), @@ -55,13 +64,6 @@ static const struct cros_gpio cros_gpios[] = { void mainboard_chromeos_acpi_generate(void) { - // TODO: MLR - // The firmware read/write status is a "virtual" switch and - // will be handled elsewhere. Until then hard-code to - // read/write instead of read-only for developer mode. - if (CONFIG(CHROMEOS_NVS)) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 2b361ac569..e0bc0b0f62 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -46,7 +46,7 @@ int get_recovery_mode_switch(void) return !get_gpio(GPIO_REC_MODE); } -static int parrot_ec_running_ro(void) +bool mainboard_ec_running_ro(void) { return get_recovery_mode_switch(); } @@ -58,9 +58,6 @@ static const struct cros_gpio cros_gpios[] = { void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && !parrot_ec_running_ro()) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 964217e8f1..fcbbc8aee0 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -49,8 +49,7 @@ int get_lid_switch(void) * The recovery-switch is virtual on Stout and is handled via the EC. * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC * indicated the recovery keys were pressed. We use a global flag for - * rec_mode to be used after RTC_POWER_STS has been cleared. This function - * is complicated by romstage support, which can't use a global variable. + * rec_mode to be used after RTC_POWER_STS has been cleared. * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. */ int get_recovery_mode_switch(void) @@ -75,6 +74,11 @@ int get_recovery_mode_switch(void) return ec_in_rec_mode; } +bool mainboard_ec_running_ro(void) +{ + return !!get_recovery_mode_switch(); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), @@ -82,8 +86,5 @@ static const struct cros_gpio cros_gpios[] = { void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && !get_recovery_mode_switch()) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 22b936c839..1b9c7c46f3 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -85,6 +85,11 @@ void init_bootmode_straps(void) pci_s_write_config32(dev, SATA_SP, flags); } +bool mainboard_ec_running_ro(void) +{ + return !ec_read(0xcb); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), @@ -92,8 +97,5 @@ static const struct cros_gpio cros_gpios[] = { void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && ec_read(0xcb)) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index abdd6c2a77..da25617121 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -25,7 +25,6 @@ void mainboard_prepare_cr50_reset(void); void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); -void chromeos_set_ecfw_rw(void); void chromeos_init_chromeos_acpi(void); /** diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 7821786979..b1090a44e9 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -31,6 +32,8 @@ static size_t chromeos_vpd_region(const char *region, uintptr_t *base) return region_device_sz(&vpd); } +__weak bool mainboard_ec_running_ro(void) { return true; } + void chromeos_init_chromeos_acpi(void) { size_t vpd_size; @@ -59,8 +62,13 @@ void chromeos_init_chromeos_acpi(void) /* EC can override to ECFW_RW. */ chromeos_acpi->vbt2 = ACTIVE_ECFW_RO; - if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) - chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_ec_running_ro()) + chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + } else { + if (!mainboard_ec_running_ro()) + chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + } } void chromeos_set_me_hash(u32 *hash, int len) @@ -83,13 +91,6 @@ void chromeos_set_ramoops(void *ram_oops, size_t size) chromeos_acpi->ramoops_len = size; } -void chromeos_set_ecfw_rw(void) -{ - if (!chromeos_acpi) - return; - chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; -} - void smbios_type0_bios_version(uintptr_t address) { if (!chromeos_acpi) -- cgit v1.2.3